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| author | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2019-05-28 21:04:29 +0000 |
|---|---|---|
| committer | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2019-05-28 21:04:29 +0000 |
| commit | 34d8daae539dfdbb3133d18b61caddd57e29adfe (patch) | |
| tree | 15bff7cff0cec5ea51338f03f1396957522b5da0 /llvm/lib | |
| parent | ccc1fa5e1d2d2c9be66aac07c3d70332d1d81adf (diff) | |
| download | bcm5719-llvm-34d8daae539dfdbb3133d18b61caddd57e29adfe.tar.gz bcm5719-llvm-34d8daae539dfdbb3133d18b61caddd57e29adfe.zip | |
[AArch64] Handle ISD::LRINT and ISD::LLRINT
This patch optimizes ISD::LRINT and ISD::LLRINT to frintx plus
fcvtzs. It currently only handles the scalar version.
Reviewed By: SjoerdMeijer, mstorsjo
Differential Revision: https://reviews.llvm.org/D62018
llvm-svn: 361877
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.td | 13 |
2 files changed, 15 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index ac656959bcb..d8e52929ffb 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -459,6 +459,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, setOperationAction(ISD::FMAXIMUM, Ty, Legal); setOperationAction(ISD::LROUND, Ty, Legal); setOperationAction(ISD::LLROUND, Ty, Legal); + setOperationAction(ISD::LRINT, Ty, Legal); + setOperationAction(ISD::LLRINT, Ty, Legal); } if (Subtarget->hasFullFP16()) { diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 8b702901d51..d9734eb3a12 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -3160,6 +3160,19 @@ let Predicates = [HasFRInt3264] in { defm FRINT64X : FRIntNNT<0b11, "frint64x">; } // HasFRInt3264 +def : Pat<(i32 (lrint f32:$Rn)), + (FCVTZSUWSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>; +def : Pat<(i32 (lrint f64:$Rn)), + (FCVTZSUWDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>; +def : Pat<(i64 (lrint f32:$Rn)), + (FCVTZSUXSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>; +def : Pat<(i64 (lrint f64:$Rn)), + (FCVTZSUXDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>; +def : Pat<(i64 (llrint f32:$Rn)), + (FCVTZSUXSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>; +def : Pat<(i64 (llrint f64:$Rn)), + (FCVTZSUXDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>; + //===----------------------------------------------------------------------===// // Floating point two operand instructions. //===----------------------------------------------------------------------===// |
