[AArch64] Handle ISD::LRINT and ISD::LLRINT

This patch optimizes ISD::LRINT and ISD::LLRINT to frintx plus
fcvtzs. It currently only handles the scalar version.

Reviewed By: SjoerdMeijer, mstorsjo

Differential Revision: https://reviews.llvm.org/D62018

llvm-svn: 361877

6 files changed, 89 insertions, 8 deletions

diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td
index 28a2eb0727a..646f945872b 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -453,6 +453,8 @@ def fround     : SDNode<"ISD::FROUND"     , SDTFPUnaryOp>;
 
 def lround     : SDNode<"ISD::LROUND"     , SDTFPToIntOp>;
 def llround    : SDNode<"ISD::LLROUND"    , SDTFPToIntOp>;
+def lrint      : SDNode<"ISD::LRINT"      , SDTFPToIntOp>;
+def llrint     : SDNode<"ISD::LLRINT"     , SDTFPToIntOp>;
 
 def fpround    : SDNode<"ISD::FP_ROUND"   , SDTFPRoundOp>;
 def fpextend   : SDNode<"ISD::FP_EXTEND"  , SDTFPExtendOp>;
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index ac656959bcb..d8e52929ffb 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -459,6 +459,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::FMAXIMUM, Ty, Legal);
     setOperationAction(ISD::LROUND, Ty, Legal);
     setOperationAction(ISD::LLROUND, Ty, Legal);
+    setOperationAction(ISD::LRINT, Ty, Legal);
+    setOperationAction(ISD::LLRINT, Ty, Legal);
   }
 
   if (Subtarget->hasFullFP16()) {
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 8b702901d51..d9734eb3a12 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3160,6 +3160,19 @@ let Predicates = [HasFRInt3264] in {
   defm FRINT64X : FRIntNNT<0b11, "frint64x">;
 } // HasFRInt3264
 
+def : Pat<(i32 (lrint f32:$Rn)),
+          (FCVTZSUWSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>;
+def : Pat<(i32 (lrint f64:$Rn)),
+          (FCVTZSUWDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>;
+def : Pat<(i64 (lrint f32:$Rn)),
+          (FCVTZSUXSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>;
+def : Pat<(i64 (lrint f64:$Rn)),
+          (FCVTZSUXDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>;
+def : Pat<(i64 (llrint f32:$Rn)),
+          (FCVTZSUXSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>;
+def : Pat<(i64 (llrint f64:$Rn)),
+          (FCVTZSUXDr (!cast<Instruction>(FRINTXDr) f64:$Rn))>;
+
 //===----------------------------------------------------------------------===//
 // Floating point two operand instructions.
 //===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/AArch64/llrint-conv.ll b/llvm/test/CodeGen/AArch64/llrint-conv.ll
index 365f6b5456d..fa11b007eeb 100644
--- a/llvm/test/CodeGen/AArch64/llrint-conv.ll
+++ b/llvm/test/CodeGen/AArch64/llrint-conv.ll
@@ -1,7 +1,9 @@
 ; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
 
 ; CHECK-LABEL: testmsws:
-; CHECK:       bl      llrintf
+; CHECK:       frintx  [[REG:s[0-9]]], s0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK:       ret
 define i32 @testmsws(float %x) {
 entry:
   %0 = tail call i64 @llvm.llrint.f32(float %x)
@@ -10,7 +12,9 @@ entry:
 }
 
 ; CHECK-LABEL: testmsxs:
-; CHECK:       b       llrintf
+; CHECK:       frintx  [[REG:s[0-9]]], s0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK-NEXT:  ret
 define i64 @testmsxs(float %x) {
 entry:
   %0 = tail call i64 @llvm.llrint.f32(float %x)
@@ -18,7 +22,9 @@ entry:
 }
 
 ; CHECK-LABEL: testmswd:
-; CHECK:       bl      llrint
+; CHECK:       frintx  [[REG:d[0-9]]], d0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK:       ret
 define i32 @testmswd(double %x) {
 entry:
   %0 = tail call i64 @llvm.llrint.f64(double %x)
@@ -27,7 +33,9 @@ entry:
 }
 
 ; CHECK-LABEL: testmsxd:
-; CHECK:       b       llrint
+; CHECK:       frintx  [[REG:d[0-9]]], d0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK-nEXT:  ret
 define i64 @testmsxd(double %x) {
 entry:
   %0 = tail call i64 @llvm.llrint.f64(double %x)
diff --git a/llvm/test/CodeGen/AArch64/lrint-conv-win.ll b/llvm/test/CodeGen/AArch64/lrint-conv-win.ll
new file mode 100644
index 00000000000..490f009c3fb
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/lrint-conv-win.ll
@@ -0,0 +1,48 @@
+; RUN: llc < %s -mtriple=aarch64-windows -mattr=+neon | FileCheck %s
+
+; CHECK-LABEL: testmsxs:
+; CHECK:       frintx  [[SREG:s[0-9]+]], s0
+; CHECK-NEXT:  fcvtzs  [[WREG:w[0-9]+]], [[SREG]]
+; CHECK-NEXT:  sxtw    x0, [[WREG]]
+; CHECK-NEXT:  ret
+define i64 @testmsxs(float %x) {
+entry:
+  %0 = tail call i32 @llvm.lrint.i32.f32(float %x)
+  %conv = sext i32 %0 to i64
+  ret i64 %conv
+}
+
+; CHECK-LABEL: testmsws:
+; CHECK:       frintx  [[SREG:s[0-9]+]], s0
+; CHECK-NEXT:  fcvtzs  [[WREG:w[0-9]+]], [[SREG]]
+; CHECK-NEXT:  ret
+define i32 @testmsws(float %x) {
+entry:
+  %0 = tail call i32 @llvm.lrint.i32.f32(float %x)
+  ret i32 %0
+}
+
+; CHECK-LABEL: testmsxd:
+; CHECK:       frintx  [[DREG:d[0-9]+]], d0
+; CHECK-NEXT:  fcvtzs  [[WREG:w[0-9]+]], [[DREG]]
+; CHECK-NEXT:  sxtw    x0, [[WREG]]
+; CHECK-NEXT:  ret
+define i64 @testmsxd(double %x) {
+entry:
+  %0 = tail call i32 @llvm.lrint.i32.f64(double %x)
+  %conv = sext i32 %0 to i64
+  ret i64 %conv
+}
+
+; CHECK-LABEL: testmswd:
+; CHECK:       frintx  [[DREG:d[0-9]+]], d0
+; CHECK-NEXT:  fcvtzs  [[WREG:w[0-9]+]], [[DREG]]
+; CHECK-NEXT:  ret
+define i32 @testmswd(double %x) {
+entry:
+  %0 = tail call i32 @llvm.lrint.i32.f64(double %x)
+  ret i32 %0
+}
+
+declare i32 @llvm.lrint.i32.f32(float) nounwind readnone
+declare i32 @llvm.lrint.i32.f64(double) nounwind readnone
diff --git a/llvm/test/CodeGen/AArch64/lrint-conv.ll b/llvm/test/CodeGen/AArch64/lrint-conv.ll
index a652de9cb3e..14d078b96ff 100644
--- a/llvm/test/CodeGen/AArch64/lrint-conv.ll
+++ b/llvm/test/CodeGen/AArch64/lrint-conv.ll
@@ -1,7 +1,9 @@
 ; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
 
 ; CHECK-LABEL: testmsws:
-; CHECK:       bl      lrintf
+; CHECK:       frintx  [[REG:s[0-9]]], s0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK:       ret
 define i32 @testmsws(float %x) {
 entry:
   %0 = tail call i64 @llvm.lrint.i64.f32(float %x)
@@ -10,7 +12,9 @@ entry:
 }
 
 ; CHECK-LABEL: testmsxs:
-; CHECK:       b       lrintf
+; CHECK:       frintx  [[REG:s[0-9]]], s0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK-NEXT:  ret
 define i64 @testmsxs(float %x) {
 entry:
   %0 = tail call i64 @llvm.lrint.i64.f32(float %x)
@@ -18,7 +22,9 @@ entry:
 }
 
 ; CHECK-LABEL: testmswd:
-; CHECK:       bl      lrint
+; CHECK:       frintx  [[REG:d[0-9]]], d0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK:       ret
 define i32 @testmswd(double %x) {
 entry:
   %0 = tail call i64 @llvm.lrint.i64.f64(double %x)
@@ -27,7 +33,9 @@ entry:
 }
 
 ; CHECK-LABEL: testmsxd:
-; CHECK:       b       lrint
+; CHECK:       frintx  [[REG:d[0-9]]], d0
+; CHECK-NEXT:  fcvtzs  x0, [[REG]]
+; CHECK-NEXT:  ret
 define i64 @testmsxd(double %x) {
 entry:
   %0 = tail call i64 @llvm.lrint.i64.f64(double %x)