diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleBtVer2.td | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td index 694d7047c0a..2fc33354fa1 100644 --- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td +++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td @@ -502,21 +502,11 @@ def : InstRW<[JWriteINSERTQ], (instrs INSERTQ, INSERTQI)>; // F16C instructions. //////////////////////////////////////////////////////////////////////////////// -def JWriteCVT3: SchedWriteRes<[JFPU1, JSTC]> { - let Latency = 3; -} -def : InstRW<[JWriteCVT3], (instrs VCVTPS2PHrr, VCVTPH2PSrr)>; - def JWriteCVT3St: SchedWriteRes<[JFPU1, JSTC, JSAGU]> { let Latency = 3; } def : InstRW<[JWriteCVT3St], (instrs VCVTPS2PHmr)>; -def JWriteCVT3Ld: SchedWriteRes<[JLAGU, JFPU1, JSTC]> { - let Latency = 8; -} -def : InstRW<[JWriteCVT3Ld], (instrs VCVTPH2PSrm)>; - def JWriteCVTPS2PHY: SchedWriteRes<[JFPU1, JSTC, JFPX]> { let Latency = 6; let ResourceCycles = [2, 2, 2]; |
