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authorQuentin Colombet <qcolombet@apple.com>2016-05-20 17:54:09 +0000
committerQuentin Colombet <qcolombet@apple.com>2016-05-20 17:54:09 +0000
commit25fcef73de76565e203efb52b2c022a2a647b735 (patch)
tree4b3e9895e5145d309ce75bd679a5dc94c6aad47e /llvm/lib
parent8818ca69dca0c6d91c0f5667306a408a1ee36204 (diff)
downloadbcm5719-llvm-25fcef73de76565e203efb52b2c022a2a647b735.tar.gz
bcm5719-llvm-25fcef73de76565e203efb52b2c022a2a647b735.zip
[RegBankSelect] Use frequency and probability information to compute
more precise cost in Greedy mode. In Fast mode the cost is irrelevant so do not bother requiring that those passes get scheduled. llvm-svn: 270244
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp35
1 files changed, 28 insertions, 7 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
index 4a052ca84cb..b244137f1ac 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
@@ -26,13 +26,18 @@
using namespace llvm;
char RegBankSelect::ID = 0;
-INITIALIZE_PASS(RegBankSelect, "regbankselect",
- "Assign register bank of generic virtual registers",
- false, false);
+INITIALIZE_PASS_BEGIN(RegBankSelect, "regbankselect",
+ "Assign register bank of generic virtual registers",
+ false, false);
+INITIALIZE_PASS_DEPENDENCY(MachineBlockFrequencyInfo)
+INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
+INITIALIZE_PASS_END(RegBankSelect, "regbankselect",
+ "Assign register bank of generic virtual registers", false,
+ false);
RegBankSelect::RegBankSelect(Mode RunningMode)
- : MachineFunctionPass(ID), RBI(nullptr), MRI(nullptr),
- OptMode(RunningMode) {
+ : MachineFunctionPass(ID), RBI(nullptr), MRI(nullptr), TRI(nullptr),
+ MBFI(nullptr), MBPI(nullptr), OptMode(RunningMode) {
initializeRegBankSelectPass(*PassRegistry::getPassRegistry());
}
@@ -41,10 +46,26 @@ void RegBankSelect::init(MachineFunction &MF) {
assert(RBI && "Cannot work without RegisterBankInfo");
MRI = &MF.getRegInfo();
TRI = MF.getSubtarget().getRegisterInfo();
- assert(OptMode == Mode::Fast && "Non-fast mode not implemented");
+ if (OptMode != Mode::Fast) {
+ MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
+ MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
+ } else {
+ MBFI = nullptr;
+ MBPI = nullptr;
+ }
MIRBuilder.setMF(MF);
}
+void RegBankSelect::getAnalysisUsage(AnalysisUsage &AU) const {
+ if (OptMode != Mode::Fast) {
+ // We could preserve the information from these two analysis but
+ // the APIs do not allow to do so yet.
+ AU.addRequired<MachineBlockFrequencyInfo>();
+ AU.addRequired<MachineBranchProbabilityInfo>();
+ }
+ MachineFunctionPass::getAnalysisUsage(AU);
+}
+
bool RegBankSelect::assignmentMatch(
unsigned Reg, const RegisterBankInfo::ValueMapping &ValMapping,
bool &OnlyAssign) const {
@@ -273,7 +294,7 @@ RegBankSelect::MappingCost RegBankSelect::computeMapping(
SmallVectorImpl<RepairingPlacement> &RepairPts) {
// If mapped with InstrMapping, MI will have the recorded cost.
- MappingCost Cost(1);
+ MappingCost Cost(MBFI ? MBFI->getBlockFreq(MI.getParent()) : 1);
bool Saturated = Cost.addLocalCost(InstrMapping.getCost());
assert(!Saturated && "Possible mapping saturated the cost");
DEBUG(dbgs() << "Evaluating mapping cost for: " << MI);
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