2 files changed, 40 insertions, 7 deletions

diff --git a/llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h b/llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
index c08c69adb6b..5d300198e15 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
@@ -71,6 +71,8 @@
 namespace llvm {
 // Forward declarations.
 class BlockFrequency;
+class MachineBranchProbabilityInfo;
+class MachineBlockFrequencyInfo;
 class MachineRegisterInfo;
 class TargetRegisterInfo;
 
@@ -460,6 +462,14 @@ private:
   /// Information on the register classes for the current function.
   const TargetRegisterInfo *TRI;
 
+  /// Get the frequency of blocks.
+  /// This is required for non-fast mode.
+  MachineBlockFrequencyInfo *MBFI;
+
+  /// Get the frequency of the edges.
+  /// This is required for non-fast mode.
+  MachineBranchProbabilityInfo *MBPI;
+
   /// Helper class used for every code morphing.
   MachineIRBuilder MIRBuilder;
 
@@ -555,6 +565,8 @@ public:
     return "RegBankSelect";
   }
 
+  void getAnalysisUsage(AnalysisUsage &AU) const override;
+
   /// Walk through \p MF and assign a register bank to every virtual register
   /// that are still mapped to nothing.
   /// The target needs to provide a RegisterBankInfo and in particular
diff --git a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
index 4a052ca84cb..b244137f1ac 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
@@ -26,13 +26,18 @@
 using namespace llvm;
 
 char RegBankSelect::ID = 0;
-INITIALIZE_PASS(RegBankSelect, "regbankselect",
-                "Assign register bank of generic virtual registers",
-                false, false);
+INITIALIZE_PASS_BEGIN(RegBankSelect, "regbankselect",
+                      "Assign register bank of generic virtual registers",
+                      false, false);
+INITIALIZE_PASS_DEPENDENCY(MachineBlockFrequencyInfo)
+INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
+INITIALIZE_PASS_END(RegBankSelect, "regbankselect",
+                    "Assign register bank of generic virtual registers", false,
+                    false);
 
 RegBankSelect::RegBankSelect(Mode RunningMode)
-    : MachineFunctionPass(ID), RBI(nullptr), MRI(nullptr),
-      OptMode(RunningMode) {
+    : MachineFunctionPass(ID), RBI(nullptr), MRI(nullptr), TRI(nullptr),
+      MBFI(nullptr), MBPI(nullptr), OptMode(RunningMode) {
   initializeRegBankSelectPass(*PassRegistry::getPassRegistry());
 }
 
@@ -41,10 +46,26 @@ void RegBankSelect::init(MachineFunction &MF) {
   assert(RBI && "Cannot work without RegisterBankInfo");
   MRI = &MF.getRegInfo();
   TRI = MF.getSubtarget().getRegisterInfo();
-  assert(OptMode == Mode::Fast && "Non-fast mode not implemented");
+  if (OptMode != Mode::Fast) {
+    MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
+    MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
+  } else {
+    MBFI = nullptr;
+    MBPI = nullptr;
+  }
   MIRBuilder.setMF(MF);
 }
 
+void RegBankSelect::getAnalysisUsage(AnalysisUsage &AU) const {
+  if (OptMode != Mode::Fast) {
+    // We could preserve the information from these two analysis but
+    // the APIs do not allow to do so yet.
+    AU.addRequired<MachineBlockFrequencyInfo>();
+    AU.addRequired<MachineBranchProbabilityInfo>();
+  }
+  MachineFunctionPass::getAnalysisUsage(AU);
+}
+
 bool RegBankSelect::assignmentMatch(
     unsigned Reg, const RegisterBankInfo::ValueMapping &ValMapping,
     bool &OnlyAssign) const {
@@ -273,7 +294,7 @@ RegBankSelect::MappingCost RegBankSelect::computeMapping(
     SmallVectorImpl<RepairingPlacement> &RepairPts) {
 
   // If mapped with InstrMapping, MI will have the recorded cost.
-  MappingCost Cost(1);
+  MappingCost Cost(MBFI ? MBFI->getBlockFreq(MI.getParent()) : 1);
   bool Saturated = Cost.addLocalCost(InstrMapping.getCost());
   assert(!Saturated && "Possible mapping saturated the cost");
   DEBUG(dbgs() << "Evaluating mapping cost for: " << MI);