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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-16 14:28:30 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-16 14:28:30 +0000 |
| commit | 22c4a147a96447b38ce90e59b27c33079f1aa203 (patch) | |
| tree | 0e170e2c2565cd25de814349e17d087783c39801 /llvm/lib | |
| parent | 8e482eb5cbb8b6839f9de701a43f1e2257ea3b34 (diff) | |
| download | bcm5719-llvm-22c4a147a96447b38ce90e59b27c33079f1aa203.tar.gz bcm5719-llvm-22c4a147a96447b38ce90e59b27c33079f1aa203.zip | |
AMDGPU/GlobalISel: Fix test failures in release build
Apparently the check for legal instructions during instruction
select does not happen without an asserts build, so these would
successfully select in release, and fail in debug.
Make s16 and/or/xor legal. These can just be selected directly
to the 32-bit operation, as is already done in SelectionDAG, so just
make them legal.
llvm-svn: 366210
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 7 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 2 |
2 files changed, 6 insertions, 3 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index fd5ee293d6c..aa634e881d8 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -291,10 +291,13 @@ bool AMDGPUInstructionSelector::selectG_AND_OR_XOR(MachineInstr &I) const { // TODO: Should this allow an SCC bank result, and produce a copy from SCC for // the result? if (DstRB->getID() == AMDGPU::SGPRRegBankID) { - const TargetRegisterClass *RC - = TRI.getConstrainedRegClassForOperand(Dst, MRI); unsigned InstOpc = getLogicalBitOpcode(I.getOpcode(), Size > 32); I.setDesc(TII.get(InstOpc)); + + const TargetRegisterClass *RC + = TRI.getConstrainedRegClassForOperand(Dst, MRI); + if (!RC) + return false; return RBI.constrainGenericRegister(DstReg, *RC, MRI) && RBI.constrainGenericRegister(Src0.getReg(), *RC, MRI) && RBI.constrainGenericRegister(Src1.getReg(), *RC, MRI); diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 3d1f7f404c9..3cf4fbc7524 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -213,7 +213,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_, // Report legal for any types we can handle anywhere. For the cases only legal // on the SALU, RegBankSelect will be able to re-legalize. getActionDefinitionsBuilder({G_AND, G_OR, G_XOR}) - .legalFor({S32, S1, S64, V2S32, V2S16, V4S16}) + .legalFor({S32, S1, S64, V2S32, S16, V2S16, V4S16}) .clampScalar(0, S32, S64) .moreElementsIf(isSmallOddVector(0), oneMoreElement(0)) .fewerElementsIf(vectorWiderThan(0, 32), fewerEltsToSize64Vector(0)) |
