1 files changed, 5 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index fd5ee293d6c..aa634e881d8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -291,10 +291,13 @@ bool AMDGPUInstructionSelector::selectG_AND_OR_XOR(MachineInstr &I) const {
   // TODO: Should this allow an SCC bank result, and produce a copy from SCC for
   // the result?
   if (DstRB->getID() == AMDGPU::SGPRRegBankID) {
-    const TargetRegisterClass *RC
-      = TRI.getConstrainedRegClassForOperand(Dst, MRI);
     unsigned InstOpc = getLogicalBitOpcode(I.getOpcode(), Size > 32);
     I.setDesc(TII.get(InstOpc));
+
+    const TargetRegisterClass *RC
+      = TRI.getConstrainedRegClassForOperand(Dst, MRI);
+    if (!RC)
+      return false;
     return RBI.constrainGenericRegister(DstReg, *RC, MRI) &&
            RBI.constrainGenericRegister(Src0.getReg(), *RC, MRI) &&
            RBI.constrainGenericRegister(Src1.getReg(), *RC, MRI);