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authorTom Stellard <thomas.stellard@amd.com>2013-08-22 20:21:02 +0000
committerTom Stellard <thomas.stellard@amd.com>2013-08-22 20:21:02 +0000
commit15e4811455565e1d695999d0febf9667c1d44e0c (patch)
tree624a8be6ba12e58b02967c393eebea5c66e78014 /llvm/lib
parent730f3c857472dd33eda184c8124da148d9de52ef (diff)
downloadbcm5719-llvm-15e4811455565e1d695999d0febf9667c1d44e0c.tar.gz
bcm5719-llvm-15e4811455565e1d695999d0febf9667c1d44e0c.zip
R600/SI: Fix another case of illegal VGPR to SGPR copy
This fixes a crash in Unigine Tropics. https://bugs.freedesktop.org/show_bug.cgi?id=68389 llvm-svn: 189057
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/R600/SIFixSGPRCopies.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/R600/SIFixSGPRCopies.cpp b/llvm/lib/Target/R600/SIFixSGPRCopies.cpp
index 435172a08ee..7f07b01f087 100644
--- a/llvm/lib/Target/R600/SIFixSGPRCopies.cpp
+++ b/llvm/lib/Target/R600/SIFixSGPRCopies.cpp
@@ -143,7 +143,7 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
}
unsigned Reg = MI.getOperand(0).getReg();
const TargetRegisterClass *RC = inferRegClass(TRI, MRI, Reg);
- if (RC == &AMDGPU::VSrc_32RegClass) {
+ if (TRI->getCommonSubClass(RC, &AMDGPU::VReg_32RegClass)) {
MRI.constrainRegClass(Reg, &AMDGPU::VReg_32RegClass);
}
}
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