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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2017-09-12 21:04:11 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2017-09-12 21:04:11 +0000 |
| commit | 106dd035a8eda70d5a43dbe3a41911e951c11a79 (patch) | |
| tree | ad8fc00a8521ea602f69f278eebf66ad201d53b3 /llvm/lib | |
| parent | a7aa2a9fb1047b1ce18c5f7eb35c424fe490eedf (diff) | |
| download | bcm5719-llvm-106dd035a8eda70d5a43dbe3a41911e951c11a79.tar.gz bcm5719-llvm-106dd035a8eda70d5a43dbe3a41911e951c11a79.zip | |
[AArch64][GlobalISel] Select all fpexts.
Tablegen already can select these: mark them as legal, remove the
c++ code, and add tests for all types.
llvm-svn: 313074
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | 27 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp | 13 |
2 files changed, 7 insertions, 33 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index 9cf9cd8b8e2..58624f24ec0 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -1180,33 +1180,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const { return selectCopy(I, TII, MRI, TRI, RBI); return false; - case TargetOpcode::G_FPEXT: { - if (MRI.getType(I.getOperand(0).getReg()) != LLT::scalar(64)) { - DEBUG(dbgs() << "G_FPEXT to type " << Ty - << ", expected: " << LLT::scalar(64) << '\n'); - return false; - } - - if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(32)) { - DEBUG(dbgs() << "G_FPEXT from type " << Ty - << ", expected: " << LLT::scalar(32) << '\n'); - return false; - } - - const unsigned DefReg = I.getOperand(0).getReg(); - const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); - - if (RB.getID() != AArch64::FPRRegBankID) { - DEBUG(dbgs() << "G_FPEXT on bank: " << RB << ", expected: FPR\n"); - return false; - } - - I.setDesc(TII.get(AArch64::FCVTDSr)); - constrainSelectedInstRegOperands(I, TII, TRI, RBI); - - return true; - } - case TargetOpcode::G_SELECT: { if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(1)) { DEBUG(dbgs() << "G_SELECT cond has type: " << Ty diff --git a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp index 9a86cac44b5..e28e43acba1 100644 --- a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp @@ -161,15 +161,16 @@ AArch64LegalizerInfo::AArch64LegalizerInfo() { setAction({G_ANYEXT, 1, Ty}, Legal); } - setAction({G_FPEXT, s64}, Legal); - setAction({G_FPEXT, 1, s32}, Legal); - - // Truncations - for (auto Ty : { s16, s32 }) + // FP conversions + for (auto Ty : { s16, s32 }) { setAction({G_FPTRUNC, Ty}, Legal); + setAction({G_FPEXT, 1, Ty}, Legal); + } - for (auto Ty : { s32, s64 }) + for (auto Ty : { s32, s64 }) { setAction({G_FPTRUNC, 1, Ty}, Legal); + setAction({G_FPEXT, Ty}, Legal); + } for (auto Ty : { s1, s8, s16, s32 }) setAction({G_TRUNC, Ty}, Legal); |

