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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2017-09-12 21:04:10 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2017-09-12 21:04:10 +0000 |
| commit | a7aa2a9fb1047b1ce18c5f7eb35c424fe490eedf (patch) | |
| tree | be65fd398958498e7ea1165707547023ab2c57b1 /llvm/lib | |
| parent | 499f58a54838dd63f8b295ec37d6de711ef270c4 (diff) | |
| download | bcm5719-llvm-a7aa2a9fb1047b1ce18c5f7eb35c424fe490eedf.tar.gz bcm5719-llvm-a7aa2a9fb1047b1ce18c5f7eb35c424fe490eedf.zip | |
[AArch64][GlobalISel] Select all fptruncs.
We already support these in tablegen, but we're matching the wrong
operator (libm ftrunc). Fix that.
While there, drop the c++ code, support COPYs of FPR16, and add tests
for the other types.
llvm-svn: 313073
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | 31 |
1 files changed, 3 insertions, 28 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index f91de078eb8..9cf9cd8b8e2 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -317,7 +317,9 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterClass *RC = nullptr; if (RegBank.getID() == AArch64::FPRRegBankID) { - if (DstSize <= 32) + if (DstSize <= 16) + RC = &AArch64::FPR16RegClass; + else if (DstSize <= 32) RC = &AArch64::FPR32RegClass; else if (DstSize <= 64) RC = &AArch64::FPR64RegClass; @@ -1205,33 +1207,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const { return true; } - case TargetOpcode::G_FPTRUNC: { - if (MRI.getType(I.getOperand(0).getReg()) != LLT::scalar(32)) { - DEBUG(dbgs() << "G_FPTRUNC to type " << Ty - << ", expected: " << LLT::scalar(32) << '\n'); - return false; - } - - if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(64)) { - DEBUG(dbgs() << "G_FPTRUNC from type " << Ty - << ", expected: " << LLT::scalar(64) << '\n'); - return false; - } - - const unsigned DefReg = I.getOperand(0).getReg(); - const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); - - if (RB.getID() != AArch64::FPRRegBankID) { - DEBUG(dbgs() << "G_FPTRUNC on bank: " << RB << ", expected: FPR\n"); - return false; - } - - I.setDesc(TII.get(AArch64::FCVTSDr)); - constrainSelectedInstRegOperands(I, TII, TRI, RBI); - - return true; - } - case TargetOpcode::G_SELECT: { if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(1)) { DEBUG(dbgs() << "G_SELECT cond has type: " << Ty |

