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| author | Diana Picus <diana.picus@linaro.org> | 2018-01-10 11:13:31 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2018-01-10 11:13:31 +0000 |
| commit | 0ed7513c83a545e3787c7b1fcf19b96affa604a3 (patch) | |
| tree | 7642ae726280bd48d2fd8fca755dbd5a86604f4d /llvm/lib | |
| parent | f949a0abace7977b5ea83dcfae70d439f6e3ebf4 (diff) | |
| download | bcm5719-llvm-0ed7513c83a545e3787c7b1fcf19b96affa604a3.tar.gz bcm5719-llvm-0ed7513c83a545e3787c7b1fcf19b96affa604a3.zip | |
[ARM GlobalISel] Map G_FNEG to the FPR bank
llvm-svn: 322169
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp index fad0e98285e..fb3553f318d 100644 --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -263,7 +263,8 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case G_FADD: case G_FSUB: case G_FMUL: - case G_FDIV: { + case G_FDIV: + case G_FNEG: { LLT Ty = MRI.getType(MI.getOperand(0).getReg()); OperandsMapping =Ty.getSizeInBits() == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] |
