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| author | Diana Picus <diana.picus@linaro.org> | 2018-01-10 11:13:31 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2018-01-10 11:13:31 +0000 |
| commit | 0ed7513c83a545e3787c7b1fcf19b96affa604a3 (patch) | |
| tree | 7642ae726280bd48d2fd8fca755dbd5a86604f4d | |
| parent | f949a0abace7977b5ea83dcfae70d439f6e3ebf4 (diff) | |
| download | bcm5719-llvm-0ed7513c83a545e3787c7b1fcf19b96affa604a3.tar.gz bcm5719-llvm-0ed7513c83a545e3787c7b1fcf19b96affa604a3.zip | |
[ARM GlobalISel] Map G_FNEG to the FPR bank
llvm-svn: 322169
| -rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir | 49 |
2 files changed, 51 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp index fad0e98285e..fb3553f318d 100644 --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -263,7 +263,8 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case G_FADD: case G_FSUB: case G_FMUL: - case G_FDIV: { + case G_FDIV: + case G_FNEG: { LLT Ty = MRI.getType(MI.getOperand(0).getReg()); OperandsMapping =Ty.getSizeInBits() == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir index 7821a65f120..049f4c60f86 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir @@ -59,6 +59,9 @@ define void @test_fdiv_s32() #0 { ret void } define void @test_fdiv_s64() #0 { ret void } + define void @test_fneg_s32() #0 { ret void } + define void @test_fneg_s64() #0 { ret void } + define void @test_soft_fp_s64() #0 { ret void } attributes #0 = { "target-features"="+vfp2"} @@ -1093,6 +1096,52 @@ body: | ... --- +name: test_fneg_s32 +# CHECK-LABEL: name: test_fneg_s32 +legalized: true +regBankSelected: false +selected: false +# CHECK: registers: +# CHECK: - { id: 0, class: fprb, preferred-register: '' } +# CHECK: - { id: 1, class: fprb, preferred-register: '' } + +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0: + liveins: %s0 + + %0(s32) = COPY %s0 + %1(s32) = G_FNEG %0 + %s0 = COPY %1(s32) + BX_RET 14, %noreg, implicit %s0 + +... +--- +name: test_fneg_s64 +# CHECK-LABEL: name: test_fneg_s64 +legalized: true +regBankSelected: false +selected: false +# CHECK: registers: +# CHECK: - { id: 0, class: fprb, preferred-register: '' } +# CHECK: - { id: 1, class: fprb, preferred-register: '' } + +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0: + liveins: %d0 + + %0(s64) = COPY %d0 + %1(s64) = G_FNEG %0 + %d0 = COPY %1(s64) + BX_RET 14, %noreg, implicit %d0 + +... +--- name: test_soft_fp_s64 # CHECK-LABEL: name: test_soft_fp_s64 legalized: true |
