[InstCombine] enable (X >>?,exact C1) << C2 --> X << (C2 - C1) for vectors with splats

llvm-svn: 293435

1 files changed, 17 insertions, 17 deletions

diff --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
index 6507bb94519..f6bede8fbb2 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
@@ -373,21 +373,6 @@ foldShiftByConstOfShiftByConst(BinaryOperator &I, const APInt *COp1,
   if (ShiftAmt1 < ShiftAmt2) {
     uint32_t ShiftDiff = ShiftAmt2 - ShiftAmt1;
 
-    // (X >>?,exact C1) << C2 --> X << (C2-C1)
-    // The inexact version is deferred to DAGCombine so we don't hide shl
-    // behind a bit mask.
-    if (I.getOpcode() == Instruction::Shl &&
-        ShiftOp->getOpcode() != Instruction::Shl && ShiftOp->isExact()) {
-      assert(ShiftOp->getOpcode() == Instruction::LShr ||
-             ShiftOp->getOpcode() == Instruction::AShr);
-      ConstantInt *ShiftDiffCst = ConstantInt::get(Ty, ShiftDiff);
-      BinaryOperator *NewShl =
-          BinaryOperator::Create(Instruction::Shl, X, ShiftDiffCst);
-      NewShl->setHasNoUnsignedWrap(I.hasNoUnsignedWrap());
-      NewShl->setHasNoSignedWrap(I.hasNoSignedWrap());
-      return NewShl;
-    }
-
     // (X << C1) >>u C2  --> X >>u (C2-C1) & (-1 >> C2)
     if (I.getOpcode() == Instruction::LShr &&
         ShiftOp->getOpcode() == Instruction::Shl) {
@@ -702,6 +687,7 @@ Instruction *InstCombiner::visitShl(BinaryOperator &I) {
   if (match(Op1, m_APInt(ShAmtAPInt))) {
     unsigned ShAmt = ShAmtAPInt->getZExtValue();
     unsigned BitWidth = I.getType()->getScalarSizeInBits();
+    Type *Ty = I.getType();
 
     // shl (zext X), ShAmt --> zext (shl X, ShAmt)
     // This is only valid if X would have zeros shifted out.
@@ -710,13 +696,27 @@ Instruction *InstCombiner::visitShl(BinaryOperator &I) {
       unsigned SrcWidth = X->getType()->getScalarSizeInBits();
       if (ShAmt < SrcWidth &&
           MaskedValueIsZero(X, APInt::getHighBitsSet(SrcWidth, ShAmt), 0, &I))
-        return new ZExtInst(Builder->CreateShl(X, ShAmt), I.getType());
+        return new ZExtInst(Builder->CreateShl(X, ShAmt), Ty);
     }
 
     // (X >>u C) << C --> X & (-1 << C)
     if (match(Op0, m_LShr(m_Value(X), m_Specific(Op1)))) {
       APInt Mask(APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt));
-      return BinaryOperator::CreateAnd(X, ConstantInt::get(I.getType(), Mask));
+      return BinaryOperator::CreateAnd(X, ConstantInt::get(Ty, Mask));
+    }
+
+    const APInt *ShrAmt;
+    if (match(Op0, m_CombineOr(m_Exact(m_LShr(m_Value(X), m_APInt(ShrAmt))),
+                               m_Exact(m_AShr(m_Value(X), m_APInt(ShrAmt))))) &&
+        ShrAmt->ult(*ShAmtAPInt)) {
+      // If C1 < C2: (X >>?,exact C1) << C2 --> X << (C2 - C1)
+      // The inexact version is deferred to DAGCombine, so we don't hide shl
+      // behind a bit mask.
+      Constant *ShiftDiffCst = ConstantInt::get(Ty, *ShAmtAPInt - *ShrAmt);
+      auto *NewShl = BinaryOperator::Create(Instruction::Shl, X, ShiftDiffCst);
+      NewShl->setHasNoUnsignedWrap(I.hasNoUnsignedWrap());
+      NewShl->setHasNoSignedWrap(I.hasNoSignedWrap());
+      return NewShl;
     }
 
     // If the shifted-out value is known-zero, then this is a NUW shift.