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| author | Ehsan Amiri <amehsan@ca.ibm.com> | 2016-11-18 11:05:55 +0000 |
|---|---|---|
| committer | Ehsan Amiri <amehsan@ca.ibm.com> | 2016-11-18 11:05:55 +0000 |
| commit | ff0942e6ea3111792bc2fbf3d2bbdc7c74937ce5 (patch) | |
| tree | 241fa35fbe1ab981101a684b2dcd3731e45eb386 /llvm/lib/Target | |
| parent | e995a8088df3798762dcff9fa4008a3c342c54de (diff) | |
| download | bcm5719-llvm-ff0942e6ea3111792bc2fbf3d2bbdc7c74937ce5.tar.gz bcm5719-llvm-ff0942e6ea3111792bc2fbf3d2bbdc7c74937ce5.zip | |
[Power9] Add patterns for vnegd, vnegw
Exploit new instructions by adding patterns to .td file.
https://reviews.llvm.org/D26551
llvm-svn: 287334
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrAltivec.td | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td index f9a500bea17..a2787f88329 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td @@ -1315,8 +1315,13 @@ let isCodeGenOnly = 1 in { } // Vector Integer Negate -def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw", []>; -def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd", []>; +def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw", + [(set v4i32:$vD, + (sub (v4i32 immAllZerosV), v4i32:$vB))]>; + +def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd", + [(set v2i64:$vD, + (sub (v2i64 (bitconvert (v4i32 immAllZerosV))), v2i64:$vB))]>; // Vector Parity Byte def VPRTYBW : VX_VT5_EO5_VB5<1538, 8, "vprtybw", [(set v4i32:$vD, |
