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| author | Craig Topper <craig.topper@intel.com> | 2018-02-27 03:50:00 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-02-27 03:50:00 +0000 |
| commit | fcaa0323ec092c6c6ccca78bc05100b41189cdb0 (patch) | |
| tree | 6472c969cb33a058700821be9cf2dc1340a0d3e7 /llvm/lib/Target | |
| parent | 883b6ee70a70ec988920666acf916c67c7337afc (diff) | |
| download | bcm5719-llvm-fcaa0323ec092c6c6ccca78bc05100b41189cdb0.tar.gz bcm5719-llvm-fcaa0323ec092c6c6ccca78bc05100b41189cdb0.zip | |
[X86] Replace an impossible if condition with an assert.
llvm-svn: 326167
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 8987f4aeb2f..0cb4b30f30b 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -16903,8 +16903,7 @@ SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const { } // Handle truncation of V256 to V128 using shuffles. - if (!VT.is128BitVector() || !InVT.is256BitVector()) - return SDValue(); + assert(VT.is128BitVector() && InVT.is256BitVector() && "Unexpected types!"); assert(Subtarget.hasFp256() && "256-bit vector without AVX!"); |
