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| author | Benjamin Kramer <benny.kra@googlemail.com> | 2016-01-14 14:33:04 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2016-01-14 14:33:04 +0000 |
| commit | fc1f7d893ef9127bf0580f86819999302a4f78b2 (patch) | |
| tree | a5f04d0a92e272d6f3f8052ad9baf623c16b39ce /llvm/lib/Target | |
| parent | 428d9dbaf9f916c7b618e65acbb04fe35866e146 (diff) | |
| download | bcm5719-llvm-fc1f7d893ef9127bf0580f86819999302a4f78b2.tar.gz bcm5719-llvm-fc1f7d893ef9127bf0580f86819999302a4f78b2.zip | |
[ARM] Use the efficient version of BitVector::set and a static_assert.
No functional change intended.
llvm-svn: 257766
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp index a5207705fc6..3af8c32de16 100644 --- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -167,9 +167,8 @@ getReservedRegs(const MachineFunction &MF) const { Reserved.set(ARM::R9); // Reserve D16-D31 if the subtarget doesn't support them. if (!STI.hasVFP3() || STI.hasD16()) { - assert(ARM::D31 == ARM::D16 + 15); - for (unsigned i = 0; i != 16; ++i) - Reserved.set(ARM::D16 + i); + static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!"); + Reserved.set(ARM::D16, ARM::D31 + 1); } const TargetRegisterClass *RC = &ARM::GPRPairRegClass; for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I) |
