dont' call getX86RegNum on X86::RIP, it doesn't like that. This

fixes the remaining x86-64 jit failures afaik.

llvm-svn: 95867

2 files changed, 7 insertions, 3 deletions

diff --git a/llvm/lib/Target/X86/X86CodeEmitter.cpp b/llvm/lib/Target/X86/X86CodeEmitter.cpp
index bcf3f15d423..6d5fa8da0d8 100644
--- a/llvm/lib/Target/X86/X86CodeEmitter.cpp
+++ b/llvm/lib/Target/X86/X86CodeEmitter.cpp
@@ -387,7 +387,9 @@ void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
   // If no BaseReg, issue a RIP relative instruction only if the MCE can 
   // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
   // 2-7) and absolute references.
-  unsigned BaseRegNo = BaseReg != 0 ? getX86RegNum(BaseReg) : -1U;
+  unsigned BaseRegNo = -1U;
+  if (BaseReg != 0 && BaseReg != X86::RIP)
+    BaseRegNo = getX86RegNum(BaseReg);
 
   if (// The SIB byte must be used if there is an index register.
       IndexReg.getReg() == 0 && 
diff --git a/llvm/lib/Target/X86/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/X86MCCodeEmitter.cpp
index ef1733f9939..ba1bdc7851d 100644
--- a/llvm/lib/Target/X86/X86MCCodeEmitter.cpp
+++ b/llvm/lib/Target/X86/X86MCCodeEmitter.cpp
@@ -175,8 +175,10 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
   const MCOperand &Scale    = MI.getOperand(Op+1);
   const MCOperand &IndexReg = MI.getOperand(Op+2);
   unsigned BaseReg = Base.getReg();
-  unsigned BaseRegNo = BaseReg != 0 ? GetX86RegNum(Base) : -1U;
-
+  unsigned BaseRegNo = -1U;
+  if (BaseReg != 0 && BaseReg != X86::RIP)
+    BaseRegNo = GetX86RegNum(Base);
+  
   // Determine whether a SIB byte is needed.
   // If no BaseReg, issue a RIP relative instruction only if the MCE can 
   // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table