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authorEric Christopher <echristo@gmail.com>2014-06-13 23:11:13 +0000
committerEric Christopher <echristo@gmail.com>2014-06-13 23:11:13 +0000
commitfb0c26c69664d06e813b3c720846f7a6562c56a7 (patch)
tree1c65c6eb70b43f894c24cf6828b229965fc1721e /llvm/lib/Target
parent8edda962962cf3143491e54aad2c9aa2b07d14ae (diff)
downloadbcm5719-llvm-fb0c26c69664d06e813b3c720846f7a6562c56a7.tar.gz
bcm5719-llvm-fb0c26c69664d06e813b3c720846f7a6562c56a7.zip
Remove InstrItineraryData off of the TargetMachine - it's already
on the subtarget and just forward the accessor. llvm-svn: 210955
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/ARM/ARMTargetMachine.cpp3
-rw-r--r--llvm/lib/Target/ARM/ARMTargetMachine.h5
2 files changed, 2 insertions, 6 deletions
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 79313fa7ad5..e55adfa0378 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -52,8 +52,7 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
CodeGenOpt::Level OL,
bool isLittle)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
- Subtarget(TT, CPU, FS, isLittle, Options),
- InstrItins(Subtarget.getInstrItineraryData()) {
+ Subtarget(TT, CPU, FS, isLittle, Options) {
// Default to triple-appropriate float ABI
if (Options.FloatABIType == FloatABI::Default)
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.h b/llvm/lib/Target/ARM/ARMTargetMachine.h
index 986789be8dd..4100d2e0268 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.h
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.h
@@ -32,9 +32,6 @@ namespace llvm {
class ARMBaseTargetMachine : public LLVMTargetMachine {
protected:
ARMSubtarget Subtarget;
-private:
- InstrItineraryData InstrItins;
-
public:
ARMBaseTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
@@ -49,7 +46,7 @@ public:
llvm_unreachable("getTargetLowering not implemented");
}
const InstrItineraryData *getInstrItineraryData() const override {
- return &InstrItins;
+ return &getSubtargetImpl()->getInstrItineraryData();
}
/// \brief Register ARM analysis passes with a pass manager.
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