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| author | Vincent Lejeune <vljn@ovi.com> | 2013-10-13 17:56:10 +0000 |
|---|---|---|
| committer | Vincent Lejeune <vljn@ovi.com> | 2013-10-13 17:56:10 +0000 |
| commit | fa58a5fb609add6c1ff6cfa7b2bf8bdc32b3c9ca (patch) | |
| tree | e333458d3259ef8e24ddc31faf4d429f806a26ff /llvm/lib/Target | |
| parent | 301beb80d42e4aebcbfb9836210ecf61873143cd (diff) | |
| download | bcm5719-llvm-fa58a5fb609add6c1ff6cfa7b2bf8bdc32b3c9ca.tar.gz bcm5719-llvm-fa58a5fb609add6c1ff6cfa7b2bf8bdc32b3c9ca.zip | |
R600: Use masked read sel for texture instructions
llvm-svn: 192554
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/R600/R600ISelLowering.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/R600ISelLowering.cpp b/llvm/lib/Target/R600/R600ISelLowering.cpp index 81a28be104a..3c2e3888e08 100644 --- a/llvm/lib/Target/R600/R600ISelLowering.cpp +++ b/llvm/lib/Target/R600/R600ISelLowering.cpp @@ -1379,6 +1379,11 @@ CompactSwizzlableVector(SelectionDAG &DAG, SDValue VectorEntry, }; for (unsigned i = 0; i < 4; i++) { + if (NewBldVec[i].getOpcode() == ISD::UNDEF) + // We mask write here to teach later passes that the ith element of this + // vector is undef. Thus we can use it to reduce 128 bits reg usage, + // break false dependencies and additionnaly make assembly easier to read. + RemapSwizzle[i] = 7; // SEL_MASK_WRITE if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(NewBldVec[i])) { if (C->isZero()) { RemapSwizzle[i] = 4; // SEL_0 |
