These targets don't like setcc

llvm-svn: 21884

2 files changed, 6 insertions, 0 deletions

diff --git a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
index 536a07710de..3281313617d 100644
--- a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
+++ b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
@@ -43,6 +43,9 @@ namespace {
     int ReturnAddrIndex;              // FrameIndex for return slot.
   public:
     PPC32TargetLowering(TargetMachine &TM) : TargetLowering(TM) {
+      // Fold away setcc operations if possible.
+      setSetCCIsExpensive();
+
       // Set up the register classes.
       addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
       addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
diff --git a/llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp
index 54f540fcf1e..a654adced92 100644
--- a/llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp
+++ b/llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp
@@ -41,6 +41,9 @@ namespace {
     int ReturnAddrIndex;              // FrameIndex for return slot.
   public:
     PPC64TargetLowering(TargetMachine &TM) : TargetLowering(TM) {
+      // Fold away setcc operations if possible.
+      setSetCCIsExpensive();
+
       // Set up the register classes.
       addRegisterClass(MVT::i64, PPC64::GPRCRegisterClass);
       addRegisterClass(MVT::f32, PPC64::FPRCRegisterClass);