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| author | Craig Topper <craig.topper@intel.com> | 2017-12-09 23:10:59 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-12-09 23:10:59 +0000 |
| commit | f4e3044db99adc2043bb351da5418ef6af920ca2 (patch) | |
| tree | 0e5f956786efdb422e91a5044e26b4a073fca41b /llvm/lib/Target | |
| parent | 5ac75d5628a1758c37e5e2c4f6ee229d399f9331 (diff) | |
| download | bcm5719-llvm-f4e3044db99adc2043bb351da5418ef6af920ca2.tar.gz bcm5719-llvm-f4e3044db99adc2043bb351da5418ef6af920ca2.zip | |
[X86] Use KMOV instructions to zero upper bits of vectors when possible.
llvm-svn: 320268
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrVecCompiler.td | 41 |
1 files changed, 29 insertions, 12 deletions
diff --git a/llvm/lib/Target/X86/X86InstrVecCompiler.td b/llvm/lib/Target/X86/X86InstrVecCompiler.td index 900ce6eb7cf..c1cb4dcb16b 100644 --- a/llvm/lib/Target/X86/X86InstrVecCompiler.td +++ b/llvm/lib/Target/X86/X86InstrVecCompiler.td @@ -495,13 +495,19 @@ let Predicates = [HasBWI, HasVLX] in { // If the bits are not zero we have to fall back to explicitly zeroing by // using shifts. -let Predicates = [HasAVX512] in { +let Predicates = [HasAVX512, NoDQI] in { def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), (v8i1 VK8:$mask), (iPTR 0))), (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK8:$mask, VK16), (i8 8)), (i8 8))>; } +let Predicates = [HasDQI] in { + def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV), + (v8i1 VK8:$mask), (iPTR 0))), + (COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK16)>; +} + let Predicates = [HasVLX, HasDQI] in { def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV), (v2i1 VK2:$mask), (iPTR 0))), @@ -526,26 +532,37 @@ let Predicates = [HasVLX] in { let Predicates = [HasBWI] in { def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + (v16i1 VK16:$mask), (iPTR 0))), + (COPY_TO_REGCLASS (KMOVWkk VK16:$mask), VK32)>; + + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + (v16i1 VK16:$mask), (iPTR 0))), + (COPY_TO_REGCLASS (KMOVWkk VK16:$mask), VK64)>; + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), + (v32i1 VK32:$mask), (iPTR 0))), + (COPY_TO_REGCLASS (KMOVDkk VK32:$mask), VK64)>; +} + +let Predicates = [HasBWI, NoDQI] in { + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), (v8i1 VK8:$mask), (iPTR 0))), (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK8:$mask, VK32), (i8 24)), (i8 24))>; - def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), - (v16i1 VK16:$mask), (iPTR 0))), - (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK16:$mask, VK32), - (i8 16)), (i8 16))>; def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), (v8i1 VK8:$mask), (iPTR 0))), (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK8:$mask, VK64), (i8 56)), (i8 56))>; +} + +let Predicates = [HasBWI, HasDQI] in { + def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV), + (v8i1 VK8:$mask), (iPTR 0))), + (COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK32)>; + def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), - (v16i1 VK16:$mask), (iPTR 0))), - (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK16:$mask, VK64), - (i8 48)), (i8 48))>; - def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV), - (v32i1 VK32:$mask), (iPTR 0))), - (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK32:$mask, VK64), - (i8 32)), (i8 32))>; + (v8i1 VK8:$mask), (iPTR 0))), + (COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK64)>; } let Predicates = [HasBWI, HasVLX] in { |
