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authorJakub Staszak <kubastaszak@gmail.com>2012-11-15 19:40:29 +0000
committerJakub Staszak <kubastaszak@gmail.com>2012-11-15 19:40:29 +0000
commitf34e4fa7a6cf6e7f7bbb42bb51f4fc36f7de04e2 (patch)
tree2b5434e025ce2cefffc52279c3aedc2a1ed07187 /llvm/lib/Target
parent824e7c0dfb93128cb317b391abf4b1448e6273c6 (diff)
downloadbcm5719-llvm-f34e4fa7a6cf6e7f7bbb42bb51f4fc36f7de04e2.tar.gz
bcm5719-llvm-f34e4fa7a6cf6e7f7bbb42bb51f4fc36f7de04e2.zip
Return 0 instead of false.
llvm-svn: 168076
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/X86/X86FastISel.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp
index 51bea7350a3..3286d7a1d7e 100644
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -2154,13 +2154,13 @@ unsigned X86FastISel::TargetMaterializeAlloca(const AllocaInst *C) {
unsigned X86FastISel::TargetMaterializeFloatZero(const ConstantFP *CF) {
MVT VT;
if (!isTypeLegal(CF->getType(), VT))
- return false;
+ return 0;
// Get opcode and regclass for the given zero.
unsigned Opc = 0;
const TargetRegisterClass *RC = NULL;
switch (VT.SimpleTy) {
- default: return false;
+ default: return 0;
case MVT::f32:
if (X86ScalarSSEf32) {
Opc = X86::FsFLD0SS;
@@ -2181,7 +2181,7 @@ unsigned X86FastISel::TargetMaterializeFloatZero(const ConstantFP *CF) {
break;
case MVT::f80:
// No f80 support yet.
- return false;
+ return 0;
}
unsigned ResultReg = createResultReg(RC);
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