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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-06-07 12:16:31 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-06-07 12:16:31 +0000 |
| commit | f1c868ef08b1de62f95cf3e51956a5394803c2ab (patch) | |
| tree | 94fc213945150422597d4775bb2e30f82a78a9be /llvm/lib/Target | |
| parent | 0e29d8d81faa33c683412cd203c208e2b434682a (diff) | |
| download | bcm5719-llvm-f1c868ef08b1de62f95cf3e51956a5394803c2ab.tar.gz bcm5719-llvm-f1c868ef08b1de62f95cf3e51956a5394803c2ab.zip | |
AMDGPU: Fix not including v2f64 in SReg_128
Fixes assertion with calls returning v2f64.
llvm-svn: 334189
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td index 0c93125a58a..e894a3da513 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td @@ -404,7 +404,7 @@ def Pseudo_SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], let CopyCost = -1; } -def Pseudo_SReg_128 : RegisterClass<"AMDGPU", [v4i32, v2i64], 32, +def Pseudo_SReg_128 : RegisterClass<"AMDGPU", [v4i32, v2i64, v2f64], 32, (add PRIVATE_RSRC_REG)> { let isAllocatable = 0; let CopyCost = -1; @@ -467,7 +467,7 @@ def TTMP_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add TTMP_128R let isAllocatable = 0; } -def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, +def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64, v2f64], 32, (add SGPR_128, TTMP_128)> { let AllocationPriority = 10; } |
