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authorPetar Jovanovic <petar.jovanovic@mips.com>2018-07-17 14:57:46 +0000
committerPetar Jovanovic <petar.jovanovic@mips.com>2018-07-17 14:57:46 +0000
commitf10e4798b4d9f5d52da9c004341b7c98727638f8 (patch)
tree65a7b239882405878254ffa266f027912dd02df0 /llvm/lib/Target
parent46ae0afba7bc80389095335da5dbed63bf3d7ba9 (diff)
downloadbcm5719-llvm-f10e4798b4d9f5d52da9c004341b7c98727638f8.tar.gz
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[Mips][FastISel] Fix handling of icmp with i1 type
The Mips FastISel back-end does not extend i1 values while lowering icmp. Ensure that we bail into DAG ISel when handling this case. Patch by Dragan Mladjenovic. Differential Revision: https://reviews.llvm.org/D49290 llvm-svn: 337288
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/Mips/MipsFastISel.cpp4
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp
index 3b0edfe0b63..7b39507812e 100644
--- a/llvm/lib/Target/Mips/MipsFastISel.cpp
+++ b/llvm/lib/Target/Mips/MipsFastISel.cpp
@@ -2062,6 +2062,10 @@ unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
if (VReg == 0)
return 0;
MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT();
+
+ if (VMVT == MVT::i1)
+ return 0;
+
if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
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