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| author | Chris Lattner <sabre@nondot.org> | 2005-10-15 21:40:12 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-10-15 21:40:12 +0000 |
| commit | efa382616b38aad28ed16a169e1a56ecd51b62ce (patch) | |
| tree | 3aea459f31d28e82cd33de36e2b412979361299d /llvm/lib/Target | |
| parent | 6b22d2554a9481b27195c650ce02997343520f10 (diff) | |
| download | bcm5719-llvm-efa382616b38aad28ed16a169e1a56ecd51b62ce.tar.gz bcm5719-llvm-efa382616b38aad28ed16a169e1a56ecd51b62ce.zip | |
remove dead code
llvm-svn: 23749
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 8396da66db2..48e6a21c76b 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -233,7 +233,7 @@ static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask, if (IsShiftMask) Mask = Mask << Shift; // determine which bits are made indeterminant by shift Indeterminant = ~(0xFFFFFFFFu << Shift); - } else if (Opcode == ISD::SRA || Opcode == ISD::SRL) { + } else if (Opcode == ISD::SRL) { // apply shift right to mask if it comes first if (IsShiftMask) Mask = Mask >> Shift; // determine which bits are made indeterminant by shift @@ -1277,13 +1277,8 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) { return SDOperand(N, 0); } case ISD::SRA: { - unsigned Imm, SH, MB, ME; - if (0 &&isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) && - isRotateAndMask(N, Imm, true, SH, MB, ME)) - CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, - Select(N->getOperand(0).getOperand(0)), - getI32Imm(SH), getI32Imm(MB), getI32Imm(ME)); - else if (isIntImmediate(N->getOperand(1), Imm)) + unsigned Imm; + if (isIntImmediate(N->getOperand(1), Imm)) CurDAG->SelectNodeTo(N, PPC::SRAWI, MVT::i32, Select(N->getOperand(0)), getI32Imm(Imm)); else |

