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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-12-15 19:43:44 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-12-15 19:43:44 +0000 |
| commit | ef7b5949e5c35fdeefb69b8f9a8eef9cfa012ed0 (patch) | |
| tree | dfb999193efcf682c3307347f2d3b831a9f49587 /llvm/lib/Target | |
| parent | 53c8b1b6f742eeac78995f1257146f504b64314a (diff) | |
| download | bcm5719-llvm-ef7b5949e5c35fdeefb69b8f9a8eef9cfa012ed0.tar.gz bcm5719-llvm-ef7b5949e5c35fdeefb69b8f9a8eef9cfa012ed0.zip | |
[X86] Lower to SHLD/SHRD on slow machines for optsize
Use consistent rules for when to lower to SHLD/SHRD for slow machines - fixes a weird issue where funnel shift gets expanded but then X86ISelLowering's combineOr sees the optsize and combines to SHLD/SHRD, but now with the modulo amount guard......
llvm-svn: 349285
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 3c1e52dec28..72d1fb00fc9 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -17047,9 +17047,9 @@ static SDValue LowerFunnelShift(SDValue Op, const X86Subtarget &Subtarget, SDValue Op1 = Op.getOperand(1); SDValue Amt = Op.getOperand(2); - // Expand slow SHLD/SHRD cases. - // TODO - can we be more selective here: OptSize/RMW etc.? - if (Subtarget.isSHLDSlow()) + // Expand slow SHLD/SHRD cases if we are not optimizing for size. + bool OptForSize = DAG.getMachineFunction().getFunction().optForSize(); + if (!OptForSize && Subtarget.isSHLDSlow()) return SDValue(); bool IsFSHR = Op.getOpcode() == ISD::FSHR; |
