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authorKristof Beyls <kristof.beyls@arm.com>2017-06-28 07:07:03 +0000
committerKristof Beyls <kristof.beyls@arm.com>2017-06-28 07:07:03 +0000
commiteecb353d0e25bae018bad815f9169c73666af5bd (patch)
tree6ff0e4920f837efd600ae00ba9dbaa896d552792 /llvm/lib/Target
parent7a82cffd68bccfea62762873375e30503dcc0bf8 (diff)
downloadbcm5719-llvm-eecb353d0e25bae018bad815f9169c73666af5bd.tar.gz
bcm5719-llvm-eecb353d0e25bae018bad815f9169c73666af5bd.zip
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
The benchmarking summarized in http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed this is beneficial for a wide range of cores. As is to be expected, quite a few small adaptations are needed to the regressions tests, as the difference in scheduling results in: - Quite a few small instruction schedule differences. - A few changes in register allocation decisions caused by different instruction schedules. - A few changes in IfConversion decisions, due to a difference in instruction schedule and/or the estimated cost of a branch mispredict. llvm-svn: 306514
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/ARM/ARM.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index 6f67183df6a..840600914b1 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -540,7 +540,7 @@ def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>;
//
// Dummy CPU, used to target architectures
-def : ProcNoItin<"generic", []>;
+def : ProcessorModel<"generic", CortexA8Model, []>;
def : ProcNoItin<"arm8", [ARMv4]>;
def : ProcNoItin<"arm810", [ARMv4]>;
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