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| author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-07-28 01:26:43 +0000 |
|---|---|---|
| committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-07-28 01:26:43 +0000 |
| commit | eca99c4b5ad19c8c7d5bcbb61713db07cb78560b (patch) | |
| tree | f411c2f1ea83b86d186a9c0e618a6164f9e81043 /llvm/lib/Target | |
| parent | 9e2a301216df4f56f9fc904f1ff3e7b113efdfd5 (diff) | |
| download | bcm5719-llvm-eca99c4b5ad19c8c7d5bcbb61713db07cb78560b.tar.gz bcm5719-llvm-eca99c4b5ad19c8c7d5bcbb61713db07cb78560b.zip | |
Add a few patterns to match allzeros without having to use the fp unit.
Take advantage that the 128-bit vpxor zeros the higher part and use it.
This also fixes PR10491
llvm-svn: 136321
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index e15d7bd76b8..cb4dbcc9691 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -2098,6 +2098,16 @@ def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>; def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))), (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>; +// AVX has no support for 256-bit integer instructions, but since the 128-bit +// VPXOR instruction writes zero to its upper part, it's safe build zeros. +def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>; +def : Pat<(bc_v8i32 (v8f32 immAllZerosV)), + (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>; + +def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>; +def : Pat<(bc_v4i64 (v8f32 immAllZerosV)), + (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>; + //===----------------------------------------------------------------------===// // SSE 1 & 2 - Load/Store XCSR register //===----------------------------------------------------------------------===// |
