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| author | Toma Tabacu <toma.tabacu@imgtec.com> | 2015-05-14 10:53:40 +0000 |
|---|---|---|
| committer | Toma Tabacu <toma.tabacu@imgtec.com> | 2015-05-14 10:53:40 +0000 |
| commit | ec1de82213c776f81c5306a4e12825e081ad6e74 (patch) | |
| tree | 7e3e801c8022d88070fa5c7e46886ff01fafd8b3 /llvm/lib/Target | |
| parent | b5592eeb0062c057d06cdd693366bc67b4e45a39 (diff) | |
| download | bcm5719-llvm-ec1de82213c776f81c5306a4e12825e081ad6e74.tar.gz bcm5719-llvm-ec1de82213c776f81c5306a4e12825e081ad6e74.zip | |
[mips] [IAS] Warn when LA is used with a 64-bit symbol.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D9295
llvm-svn: 237356
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index b757b2448e7..45169b70513 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -195,7 +195,8 @@ class MipsAsmParser : public MCTargetAsmParser { SmallVectorImpl<MCInst> &Instructions); void expandLoadAddressSym(const MCOperand &DstRegOp, const MCOperand &SymOp, - SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions); + bool Is32BitSym, SMLoc IDLoc, + SmallVectorImpl<MCInst> &Instructions); void expandMemInst(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions, bool isLoad, @@ -1876,7 +1877,7 @@ MipsAsmParser::expandLoadAddressReg(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, assert((ImmOp.isImm() || ImmOp.isExpr()) && "expected immediate operand kind"); if (!ImmOp.isImm()) { - expandLoadAddressSym(DstRegOp, ImmOp, IDLoc, Instructions); + expandLoadAddressSym(DstRegOp, ImmOp, Is32BitImm, IDLoc, Instructions); return false; } const MCOperand &SrcRegOp = Inst.getOperand(1); @@ -1899,7 +1900,7 @@ MipsAsmParser::expandLoadAddressImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, assert((ImmOp.isImm() || ImmOp.isExpr()) && "expected immediate operand kind"); if (!ImmOp.isImm()) { - expandLoadAddressSym(DstRegOp, ImmOp, IDLoc, Instructions); + expandLoadAddressSym(DstRegOp, ImmOp, Is32BitImm, IDLoc, Instructions); return false; } @@ -1910,10 +1911,12 @@ MipsAsmParser::expandLoadAddressImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, return false; } -void -MipsAsmParser::expandLoadAddressSym(const MCOperand &DstRegOp, - const MCOperand &SymOp, SMLoc IDLoc, - SmallVectorImpl<MCInst> &Instructions) { +void MipsAsmParser::expandLoadAddressSym( + const MCOperand &DstRegOp, const MCOperand &SymOp, bool Is32BitSym, + SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) { + if (Is32BitSym && isABI_N64()) + Warning(IDLoc, "instruction loads the 32-bit address of a 64-bit symbol"); + MCInst tmpInst; unsigned RegNo = DstRegOp.getReg(); const MCSymbolRefExpr *Symbol = cast<MCSymbolRefExpr>(SymOp.getExpr()); @@ -1923,7 +1926,7 @@ MipsAsmParser::expandLoadAddressSym(const MCOperand &DstRegOp, const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(Symbol->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_LO, getContext()); - if (isGP64bit()) { + if (!Is32BitSym) { // If it's a 64-bit architecture, expand to: // la d,sym => lui d,highest(sym) // ori d,d,higher(sym) |
