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| author | Craig Topper <craig.topper@intel.com> | 2018-04-29 04:50:53 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-04-29 04:50:53 +0000 |
| commit | ebd3e4a69cb52af96ec9529a35536b2cd0657298 (patch) | |
| tree | 422900e87561c029f7c9740687fbba67cfcce9df /llvm/lib/Target | |
| parent | 8e3dbfd725eb8283deaf27cccff0993d09bbb99d (diff) | |
| download | bcm5719-llvm-ebd3e4a69cb52af96ec9529a35536b2cd0657298.tar.gz bcm5719-llvm-ebd3e4a69cb52af96ec9529a35536b2cd0657298.zip | |
[X86] Remove SLDT64m instruction.
It doesn't really exist. The instruction always writes 16-bits of memory. Putting a REX.w on it won't change anything.
While I was touching the encoding tests to remove it, I added some other missing register form test cases.
llvm-svn: 331135
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSystem.td | 3 | ||||
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedBroadwell.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedHaswell.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSkylakeClient.td | 1 | ||||
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedSkylakeServer.td | 1 |
5 files changed, 0 insertions, 7 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSystem.td b/llvm/lib/Target/X86/X86InstrSystem.td index 3e9c264a693..190f2958876 100644 --- a/llvm/lib/Target/X86/X86InstrSystem.td +++ b/llvm/lib/Target/X86/X86InstrSystem.td @@ -382,9 +382,6 @@ def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins), // extension. def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins), "sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>; -let mayStore = 1 in -def SLDT64m : RI<0x00, MRM0m, (outs), (ins i16mem:$dst), - "sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>; def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src), "lgdt{w}\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>; diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td index c07d68f8c94..9ae398141fb 100755 --- a/llvm/lib/Target/X86/X86SchedBroadwell.td +++ b/llvm/lib/Target/X86/X86SchedBroadwell.td @@ -455,7 +455,6 @@ def: InstRW<[BWWriteResGroup9], (instregex "LAHF", // TODO: This doesnt match Ag "SAHF", // TODO: This doesn't match Agner's data "SGDT64m", "SIDT64m", - "SLDT64m", "SMSW16m", "STRm", "SYSCALL")>; diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index 3066dbb22c3..964e2b1c7e0 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -786,7 +786,6 @@ def: InstRW<[HWWriteResGroup10], (instregex "CLC", "NOOP", "SGDT64m", "SIDT64m", - "SLDT64m", "SMSW16m", "STC", "STRm", diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index c52d147655d..e6608bc627b 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -539,7 +539,6 @@ def: InstRW<[SKLWriteResGroup10], (instregex "CLC", "SAHF", // TODO: This doesn't match Agner's data "SGDT64m", "SIDT64m", - "SLDT64m", "SMSW16m", "STC", "STRm", diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index 22f038292d7..00250676c04 100755 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -908,7 +908,6 @@ def: InstRW<[SKXWriteResGroup10], (instregex "CLC", "SAHF", // TODO: This doesn't match Agner's data "SGDT64m", "SIDT64m", - "SLDT64m", "SMSW16m", "STC", "STRm", |
