Implement LaneBitmask::any(), use it to replace !none(), NFCI

llvm-svn: 289974

5 files changed, 11 insertions, 11 deletions

diff --git a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
index 44637615b04..adc213c3d43 100644
--- a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
@@ -240,7 +240,7 @@ HexagonBlockRanges::RegisterSet HexagonBlockRanges::getLiveIns(
     }
     for (MCSubRegIndexIterator S(I.PhysReg, &TRI); S.isValid(); ++S) {
       LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex());
-      if (!(M & I.LaneMask).none())
+      if ((M & I.LaneMask).any())
         Tmp.insert({S.getSubReg(), 0});
     }
   }
diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index 55978a63b92..8f070d842b8 100644
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -369,7 +369,7 @@ void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
     if (!TargetRegisterInfo::isVirtualRegister(DR) || DR != Reg)
       return false;
     LaneBitmask SLM = getLaneMask(DR, DSR);
-    return !(SLM & LM).none();
+    return (SLM & LM).any();
   };
 
   // The splitting step will create pairs of predicated definitions without
diff --git a/llvm/lib/Target/Hexagon/RDFGraph.cpp b/llvm/lib/Target/Hexagon/RDFGraph.cpp
index 04052b74a04..33c3f03790f 100644
--- a/llvm/lib/Target/Hexagon/RDFGraph.cpp
+++ b/llvm/lib/Target/Hexagon/RDFGraph.cpp
@@ -662,7 +662,7 @@ bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
   RegisterRef NR = normalize(RR);
   auto F = Masks.find(NR.Reg);
   if (F != Masks.end()) {
-    if (!(F->second & NR.Mask).none())
+    if ((F->second & NR.Mask).any())
       return true;
   }
   if (CheckUnits) {
@@ -1089,7 +1089,7 @@ RegisterRef DataFlowGraph::normalizeRef(RegisterRef RR) const {
 RegisterRef DataFlowGraph::restrictRef(RegisterRef AR, RegisterRef BR) const {
   if (AR.Reg == BR.Reg) {
     LaneBitmask M = AR.Mask & BR.Mask;
-    return !M.none() ? RegisterRef(AR.Reg, M) : RegisterRef();
+    return M.any() ? RegisterRef(AR.Reg, M) : RegisterRef();
   }
 #ifndef NDEBUG
   RegisterRef NAR = normalizeRef(AR);
@@ -1221,7 +1221,7 @@ bool DataFlowGraph::alias(RegisterRef RA, RegisterRef RB) const {
       // while the lane mask of r2 in d1 may be 0b0001.
       LaneBitmask LA = PA.second & RA.Mask;
       LaneBitmask LB = PB.second & RB.Mask;
-      if (!LA.none() && !LB.none()) {
+      if (LA.any() && LB.any()) {
         unsigned Root = *MCRegUnitRootIterator(PA.first, &TRI);
         // If register units were guaranteed to only have 1 bit in any lane
         // mask, the code below would not be necessary. This is because LA
@@ -1232,7 +1232,7 @@ bool DataFlowGraph::alias(RegisterRef RA, RegisterRef RB) const {
         const TargetRegisterClass &RC = *TRI.getMinimalPhysRegClass(Root);
         LaneBitmask MaskA = TRI.reverseComposeSubRegIndexLaneMask(SubA, LA);
         LaneBitmask MaskB = TRI.reverseComposeSubRegIndexLaneMask(SubB, LB);
-        if (!(MaskA & MaskB & RC.LaneMask).none())
+        if ((MaskA & MaskB & RC.LaneMask).any())
           return true;
       }
 
diff --git a/llvm/lib/Target/Hexagon/RDFGraph.h b/llvm/lib/Target/Hexagon/RDFGraph.h
index b279752a21f..871062ff2b0 100644
--- a/llvm/lib/Target/Hexagon/RDFGraph.h
+++ b/llvm/lib/Target/Hexagon/RDFGraph.h
@@ -405,7 +405,7 @@ namespace rdf {
     RegisterRef() : RegisterRef(0) {}
     explicit RegisterRef(RegisterId R, LaneBitmask M = LaneBitmask::getAll())
       : Reg(R), Mask(R != 0 ? M : LaneBitmask::getNone()) {}
-    operator bool() const { return Reg != 0 && !Mask.none(); }
+    operator bool() const { return Reg != 0 && Mask.any(); }
     bool operator== (const RegisterRef &RR) const {
       return Reg == RR.Reg && Mask == RR.Mask;
     }
@@ -471,11 +471,11 @@ namespace rdf {
       return K == 0 ? LaneBitmask::getAll() : get(K);
     }
     uint32_t getIndexForLaneMask(LaneBitmask LM) {
-      assert(!LM.none());
+      assert(LM.any());
       return LM.all() ? 0 : insert(LM);
     }
     uint32_t getIndexForLaneMask(LaneBitmask LM) const {
-      assert(!LM.none());
+      assert(LM.any());
       return LM.all() ? 0 : find(LM);
     }
     PackedRegisterRef pack(RegisterRef RR) {
diff --git a/llvm/lib/Target/Hexagon/RDFLiveness.cpp b/llvm/lib/Target/Hexagon/RDFLiveness.cpp
index 3563d056692..e74c4bfc164 100644
--- a/llvm/lib/Target/Hexagon/RDFLiveness.cpp
+++ b/llvm/lib/Target/Hexagon/RDFLiveness.cpp
@@ -710,7 +710,7 @@ void Liveness::computeLiveIns() {
         }
         do {
           LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex());
-          if (!(M & P.second).none())
+          if ((M & P.second).any())
             LV.push_back(RegisterRef(S.getSubReg()));
           ++S;
         } while (S.isValid());
@@ -759,7 +759,7 @@ void Liveness::resetKills(MachineBasicBlock *B) {
       }
       do {
         LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex());
-        if (!(M & I.LaneMask).none())
+        if ((M & I.LaneMask).any())
           LV.set(S.getSubReg());
         ++S;
       } while (S.isValid());