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| author | Bill Wendling <isanbard@gmail.com> | 2007-03-10 09:57:05 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2007-03-10 09:57:05 +0000 |
| commit | e9b81f5366fe631a91147473d3b9503be5ea94fe (patch) | |
| tree | 716cb7ae6989ca50899ce4a64ea93e556f68c72b /llvm/lib/Target | |
| parent | 9d1c347921b024679ff0d163daa8a53229773c93 (diff) | |
| download | bcm5719-llvm-e9b81f5366fe631a91147473d3b9503be5ea94fe.tar.gz bcm5719-llvm-e9b81f5366fe631a91147473d3b9503be5ea94fe.zip | |
Adding more arithmetic operators to MMX. This is an almost exact copy of
the addition. Please let me know if you have suggestions.
llvm-svn: 35055
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrMMX.td | 10 |
2 files changed, 14 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 2ab5e086197..4fecb70cd29 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -331,6 +331,10 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) setOperationAction(ISD::ADD, MVT::v4i16, Legal); setOperationAction(ISD::ADD, MVT::v2i32, Legal); + setOperationAction(ISD::SUB, MVT::v8i8, Legal); + setOperationAction(ISD::SUB, MVT::v4i16, Legal); + setOperationAction(ISD::SUB, MVT::v2i32, Legal); + setOperationAction(ISD::LOAD, MVT::v8i8, Promote); AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32); setOperationAction(ISD::LOAD, MVT::v4i16, Promote); diff --git a/llvm/lib/Target/X86/X86InstrMMX.td b/llvm/lib/Target/X86/X86InstrMMX.td index 5096c203bac..73f2f11a863 100644 --- a/llvm/lib/Target/X86/X86InstrMMX.td +++ b/llvm/lib/Target/X86/X86InstrMMX.td @@ -101,6 +101,16 @@ defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>; defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>; defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>; +defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>; +defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>; +defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>; + +defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>; +defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>; + +defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>; +defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>; + // Move Instructions def MOVD64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src), "movd {$src, $dst|$dst, $src}", []>; |
