* Removed unused classes (rd field is always mentioned last); fixed comments.

* Added instruction classes which start building from rs1, then rs2, and rd.
* Fixed order of operands in classes 4.1 and 4.2; added 4.6 .

llvm-svn: 6561

1 files changed, 34 insertions, 38 deletions

diff --git a/llvm/lib/Target/Sparc/SparcV9_F4.td b/llvm/lib/Target/Sparc/SparcV9_F4.td
index 7a5df8b4ed6..0f5b00e41ba 100644
--- a/llvm/lib/Target/Sparc/SparcV9_F4.td
+++ b/llvm/lib/Target/Sparc/SparcV9_F4.td
@@ -11,48 +11,35 @@ class F4 : InstV9 {
   set Inst{24-19} = op3;
 }
 
-class F4_rd : F4 {
-  bits<5> rd;
-  set Inst{29-25} = rd;
-}
-
-class F4_rdsimm11 : F4_rd {
-  bits<11> simm11;
-  set Inst{10-0} = simm11;
-}
-
-class F4_rdsimm11rs1 : F4_rdsimm11 {
-  bits<5> rs1;
-  set Inst{18-14} = rs1;
-}
-
-// F4_rdrs1 - Common superclass of instructions that use rd & rs1
-class F4_rdrs1 : F4_rd {
-  bits<5> rs1;
-  set Inst{18-14} = rs1;
-}
-
-// F4_rs1rdrs2 - Common superclass of instructions with rd, rs1, & rs2 fields
-class F4_rdrs1rs2 : F4_rdrs1 {
-  bits<5> rs2;
-  set Inst{4-0} = rs2;
-}
-
-// F4_rs1 - Common class of instructions that do not have an rd field,
-// but start at rs1
+// F4_rs1 - Common class of instructions that use an rs1 field
 class F4_rs1 : F4 {
   bits<5> rs1;
   //set Inst{29-25} = dontcare;
   set Inst{18-14} = rs1;
 }
 
-// F4_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
+// F4_rs1rs2 - Common class of instructions that have rs1 and rs2 fields
 class F4_rs1rs2 : F4_rs1 {
   bits<5> rs2;
   //set Inst{12-5} = dontcare;
   set Inst{4-0} = rs2;
 }
 
+// F4_rs1rs2rd - Common class of instructions that have 3 register operands
+class F4_rs1rs2rd : F4_rs1rs2 {
+  bits<5> rd;
+  set Inst{29-25} = rd;
+}
+
+// F4_rs1rs2rd - Common class of instructions that have 2 reg and 1 imm operand
+class F4_rs1simm11rd : F4_rs1 {
+  bits<11> simm11;
+  bits<5>  rd;
+
+  set Inst{10-0}  = simm11;
+  set Inst{29-25} = rd;
+}
+
 // F4_cc - Common class of instructions that have a cond field
 class F4_cond : F4 {
   bits<4> cond;
@@ -68,9 +55,8 @@ class F4_condcc : F4_cond {
 }
 
 // Actual F4 instruction classes
-
-// FIXME: order of operands is incorrect!!
-class F4_1<bits<2> opVal, bits<6> op3Val, string name> : F4_rdrs1rs2 {
+//
+class F4_1<bits<2> opVal, bits<6> op3Val, string name> : F4_rs1rs2rd {
   bits<2> cc;
 
   set op = opVal;
@@ -81,8 +67,7 @@ class F4_1<bits<2> opVal, bits<6> op3Val, string name> : F4_rdrs1rs2 {
   //set Inst{10-5} = dontcare;
 }
 
-// FIXME: order of operands is incorrect!!
-class F4_2<bits<2> opVal, bits<6> op3Val, string name> : F4_rdsimm11rs1 {
+class F4_2<bits<2> opVal, bits<6> op3Val, string name> : F4_rs1simm11rd {
   bits<2> cc;
 
   set op = opVal;
@@ -110,13 +95,24 @@ class F4_4<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
   bits<11> sim11;
   bits<5>  rd;
 
-  set op = opVal;
-  set op3 = op3Val;
+  set op   = opVal;
+  set op3  = op3Val;
   set cond = condVal;
   set Name = name;
   set Inst{13} = 1; // i bit
   set Inst{10-0} = sim11;
 }  
   
+// FIXME: class F4_5
+
+class F4_6<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,
+           bits<5> opf_lowVal, string name> : F4_rs1rs2rd {
+  set op  = opVal;
+  set op3 = op3Val;
+  set Name = name;
+  set Inst{13} = 0;
+  set Inst{12-10} = rcondVal;
+  set Inst{9-5} = opf_lowVal;
+}
 
-// FIXME: F4 classes 4
+// FIXME: F4 classes 7-9