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| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-04-28 19:49:18 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-04-28 19:49:18 +0000 |
| commit | e5fcce2d2b0a9ff048bc8f6aa0bb776a18a671c2 (patch) | |
| tree | 1b441daf34c0f2b1b8dbf1f1c7956f820427665e /llvm/lib/Target | |
| parent | 97dc0c8c29f857fcffffc2b1ebaad459e91dc150 (diff) | |
| download | bcm5719-llvm-e5fcce2d2b0a9ff048bc8f6aa0bb776a18a671c2.tar.gz bcm5719-llvm-e5fcce2d2b0a9ff048bc8f6aa0bb776a18a671c2.zip | |
[Hexagon] Add instruction aliases for vector unsigned compare-equal
Unsigned compare-equal instructions are mapped to signed compare-equal.
llvm-svn: 267925
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonAlias.td | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonAlias.td b/llvm/lib/Target/Hexagon/HexagonAlias.td index e14e5994cb4..296c1765e2e 100644 --- a/llvm/lib/Target/Hexagon/HexagonAlias.td +++ b/llvm/lib/Target/Hexagon/HexagonAlias.td @@ -27,3 +27,68 @@ def : InstAlias<"$Vd = #0", def : InstAlias<"$Vdd = #0", (V6_vsubw_dv VecDblRegs:$Vdd, VecDblRegs:$Vdd, VecDblRegs:$Vdd)>, Requires<[HasV60T]>; + +// maps "$Qd = vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd = vcmp.eq($Vu.h, $Vv.h)" +def : InstAlias<"$Qd = vcmp.eq($Vu.uh, $Vv.uh)", + (V6_veqh VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, + Requires<[HasV60T]>; + +// maps "$Qd &= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd &= vcmp.eq($Vu.h, $Vv.h)" +def : InstAlias<"$Qd &= vcmp.eq($Vu.uh, $Vv.uh)", + (V6_veqh_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, + Requires<[HasV60T]>; + +// maps "$Qd |= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd |= vcmp.eq($Vu.h, $Vv.h)" +def : InstAlias<"$Qd |= vcmp.eq($Vu.uh, $Vv.uh)", + (V6_veqh_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, + Requires<[HasV60T]>; + +// maps "$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd ^= vcmp.eq($Vu.h, $Vv.h)" +def : InstAlias<"$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)", + (V6_veqh_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, + Requires<[HasV60T]>; + +// maps "$Qd = vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd = vcmp.eq($Vu.w, $Vv.w)" +def : InstAlias<"$Qd = vcmp.eq($Vu.uw, $Vv.uw)", + (V6_veqw VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, + Requires<[HasV60T]>; + +// maps "$Qd &= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd &= vcmp.eq($Vu.w, $Vv.w)" +def : InstAlias<"$Qd &= vcmp.eq($Vu.uw, $Vv.uw)", + (V6_veqw_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, + Requires<[HasV60T]>; + +// maps "$Qd |= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd |= vcmp.eq($Vu.w, $Vv.w)" +def : InstAlias<"$Qd |= vcmp.eq($Vu.uw, $Vv.uw)", + (V6_veqh_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, + Requires<[HasV60T]>; + +// maps "$Qd ^= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd ^= vcmp.eq($Vu.w, $Vv.w)" +def : InstAlias<"$Qd ^= vcmp.eq($Vu.uw, $Vv.uw)", + (V6_veqw_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, + Requires<[HasV60T]>; + +// maps "$Qd = vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd = vcmp.eq($Vu.b, $Vv.b)" +def : InstAlias<"$Qd = vcmp.eq($Vu.ub, $Vv.ub)", + (V6_veqb VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, + Requires<[HasV60T]>; + +// maps "$Qd &= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd &= vcmp.eq($Vu.b, $Vv.b)" +def : InstAlias<"$Qd &= vcmp.eq($Vu.ub, $Vv.ub)", + (V6_veqb_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, + Requires<[HasV60T]>; + +// maps "$Qd |= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd |= vcmp.eq($Vu.b, $Vv.b)" +def : InstAlias<"$Qd |= vcmp.eq($Vu.ub, $Vv.ub)", + (V6_veqb_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, + Requires<[HasV60T]>; + +// maps "$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd ^= vcmp.eq($Vu.b, $Vv.b)" +def : InstAlias<"$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)", + (V6_veqb_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, + Requires<[HasV60T]>; + +// maps "$Rd.w = vextract($Vu, $Rs)" -> "$Rd = vextract($Vu, $Rs)" +def : InstAlias<"$Rd.w = vextract($Vu, $Rs)", + (V6_extractw IntRegs:$Rd, VectorRegs:$Vu, IntRegs:$Rs)>, + Requires<[HasV60T]>; |
