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| author | Bill Wendling <isanbard@gmail.com> | 2010-06-25 20:48:10 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2010-06-25 20:48:10 +0000 |
| commit | e41e40f6896e4ace94f1ca9295f0177892f7dd48 (patch) | |
| tree | 67614a6543f2da410110aabb2a80dc2ddf2c3b2a /llvm/lib/Target | |
| parent | ef7acd9a24859fa01d2a69528cfbe91bb83fa3f9 (diff) | |
| download | bcm5719-llvm-e41e40f6896e4ace94f1ca9295f0177892f7dd48.tar.gz bcm5719-llvm-e41e40f6896e4ace94f1ca9295f0177892f7dd48.zip | |
- Reapply r106066 now that the bzip2 build regression has been fixed.
- 2010-06-25-CoalescerSubRegDefDead.ll is the testcase for r106878.
llvm-svn: 106880
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index bed9d1d1a82..3a850f863a9 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -8477,22 +8477,42 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); unsigned Opc = X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); + BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); F->insert(It, copy0MBB); F->insert(It, sinkMBB); + // Update machine-CFG edges by first adding all successors of the current // block to the new block which will contain the Phi node for the select. for (MachineBasicBlock::succ_iterator I = BB->succ_begin(), E = BB->succ_end(); I != E; ++I) sinkMBB->addSuccessor(*I); + // Next, remove all successors of the current block, and add the true // and fallthrough blocks as its successors. while (!BB->succ_empty()) BB->removeSuccessor(BB->succ_begin()); + // Add the true and fallthrough blocks as its successors. BB->addSuccessor(copy0MBB); BB->addSuccessor(sinkMBB); + // If the EFLAGS register isn't dead in the terminator, then claim that it's + // live into the sink and copy blocks. + const MachineFunction *MF = BB->getParent(); + const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); + BitVector ReservedRegs = TRI->getReservedRegs(*MF); + const MachineInstr *Term = BB->getFirstTerminator(); + + for (unsigned I = 0, E = Term->getNumOperands(); I != E; ++I) { + const MachineOperand &MO = Term->getOperand(I); + if (!MO.isReg() || MO.isKill() || MO.isDead()) continue; + unsigned Reg = MO.getReg(); + if (Reg != X86::EFLAGS) continue; + copy0MBB->addLiveIn(Reg); + sinkMBB->addLiveIn(Reg); + } + // copy0MBB: // %FalseValue = ... // # fallthrough to sinkMBB |

