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| author | Simon Atanasyan <simon@atanasyan.com> | 2019-07-09 15:48:16 +0000 |
|---|---|---|
| committer | Simon Atanasyan <simon@atanasyan.com> | 2019-07-09 15:48:16 +0000 |
| commit | e3892d84e0c1bf6b0e0c41e243726f3c06a1f772 (patch) | |
| tree | a574bf958d02859731f803dad771f597cd5fb99a /llvm/lib/Target | |
| parent | 623282f0dd7fb1dba7623f2b10294f003f92570e (diff) | |
| download | bcm5719-llvm-e3892d84e0c1bf6b0e0c41e243726f3c06a1f772.tar.gz bcm5719-llvm-e3892d84e0c1bf6b0e0c41e243726f3c06a1f772.zip | |
[mips] Show error in case of using FP64 mode on pre MIPS32R2 CPU
llvm-svn: 365508
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsSubtarget.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp index 472dd72de94..d021b3d021b 100644 --- a/llvm/lib/Target/Mips/MipsSubtarget.cpp +++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp @@ -108,6 +108,11 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, "See -mattr=+fp64.", false); + if (isFP64bit() && !hasMips64() && hasMips32() && !hasMips32r2()) + report_fatal_error( + "FPU with 64-bit registers is not available on MIPS32 pre revision 2. " + "Use -mcpu=mips32r2 or greater."); + if (!isABI_O32() && !useOddSPReg()) report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false); |
