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| author | Geoff Berry <gberry@codeaurora.org> | 2017-05-15 18:50:22 +0000 |
|---|---|---|
| committer | Geoff Berry <gberry@codeaurora.org> | 2017-05-15 18:50:22 +0000 |
| commit | e369653bf332cd21b2ee8eabb44febd600bccaa2 (patch) | |
| tree | 3188f6c2470799aaa3a6f3478aabb2ad2f2cdded /llvm/lib/Target | |
| parent | 0e289822fa13c554b4eb0f34527242e55e160a7e (diff) | |
| download | bcm5719-llvm-e369653bf332cd21b2ee8eabb44febd600bccaa2.tar.gz bcm5719-llvm-e369653bf332cd21b2ee8eabb44febd600bccaa2.zip | |
[AArch64][Falkor] Fix sched details for FMOV
llvm-svn: 303099
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td | 7 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td | 3 |
2 files changed, 6 insertions, 4 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td b/llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td index f5015416e4d..a9b4d44a523 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td +++ b/llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td @@ -430,10 +430,13 @@ def : InstRW<[FalkorWr_FMUL64_1VXVY_6cyc, ReadDefault, ReadDefault, FalkorReadFM // FP Miscellaneous Instructions // ----------------------------------------------------------------------------- -def : InstRW<[FalkorWr_FMOV], (instregex "^FMOV(HW|HX|SW|DX|DXHigh)r$")>; +def : InstRW<[FalkorWr_FMOV], (instregex "^FMOV(H|S|D)i$")>; +def : InstRW<[FalkorWr_1GTOV_1cyc], (instregex "^FMOV(HW|HX|SW|DX|DXHigh)r$")>; def : InstRW<[FalkorWr_1VTOG_1cyc], (instregex "^FCVTZ(S|U)(S|U)(W|X)(D|S)ri?$")>; def : InstRW<[FalkorWr_1VTOG_1cyc], (instregex "^FMOV(WH|WS|XH|XD|XDHigh)r$")>; -def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^FMOV(Hi|Hr|S0|Si|Sr|D0|Di|Dr|v.*_ns)$")>; +def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^FMOV(Hr|Sr|Dr|v.*_ns)$")>; +// FIXME: We are currently generating movi v0.2d, #0 for these, which is worse than fmov 0.0 +def : InstRW<[FalkorWr_2VXVY_1cyc], (instrs FMOVD0, FMOVS0)>; def : InstRW<[FalkorWr_1GTOV_4cyc], (instregex "^(S|U)CVTF(S|U)(W|X)(D|S)ri$")>; def : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^(S|U)CVTF(v1i16|v1i32|v2i32|v1i64|v4i16|v2f32|v4f16|d|s)(_shift)?")>; diff --git a/llvm/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td b/llvm/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td index dfee9299968..6526cc28e80 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td +++ b/llvm/lib/Target/AArch64/AArch64SchedFalkorWriteRes.td @@ -375,7 +375,7 @@ def FalkorReadFMA64 : SchedReadAdvance<2, [FalkorWr_FMUL64_1VXVY_6cyc, FalkorWr // SchedPredicates and WriteVariants for Immediate Zero and LSLFast // ----------------------------------------------------------------------------- -def FalkorImmZPred : SchedPredicate<[{TII->isGPRZero(*MI)}]>; +def FalkorImmZPred : SchedPredicate<[{MI->getOperand(1).getImm() == 0}]>; def FalkorLSLFastPred : SchedPredicate<[{TII->isFalkorLSLFast(*MI)}]>; def FalkorWr_FMOV : SchedWriteVariant<[ @@ -392,7 +392,6 @@ def FalkorWr_LDR : SchedWriteVariant<[ def FalkorWr_ADD : SchedWriteVariant<[ SchedVar<FalkorLSLFastPred, [FalkorWr_1XYZ_1cyc]>, - SchedVar<FalkorImmZPred, [FalkorWr_1XYZ_1cyc]>, SchedVar<NoSchedPred, [FalkorWr_2XYZ_2cyc]>]>; def FalkorWr_PRFM : SchedWriteVariant<[ |
