[AArch64] Use 16 bytes as preferred function alignment on Cortex-A72.

Summary:
This change gives a 0.34% speed on execution time, a 0.61% improvement
in benchmark scores and a 0.57% increase in binary size on a Cortex-A72.
These numbers are the geomean results on a wide range of benchmarks from
the test-suite, SPEC2000, SPEC2006 and a range of proprietary suites.

The software optimization guide for the Cortex-A72 recommends 16 byte
branch alignment.


Reviewers: t.p.northover, kristof.beyls, rengolin, sbaranga, mcrosier, javed.absar

Reviewed By: kristof.beyls

Subscribers: llvm-commits, aemerson

Differential Revision: https://reviews.llvm.org/D34961

llvm-svn: 307380

1 files changed, 3 insertions, 1 deletions

diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
index a9a9d5ce842..df620cc2934 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -130,7 +130,9 @@ void AArch64Subtarget::initializeProperties() {
     break;
   case CortexA35: break;
   case CortexA53: break;
-  case CortexA72: break;
+  case CortexA72:
+    PrefFunctionAlignment = 4;
+    break;
   case CortexA73: break;
   case Others: break;
   }