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| author | Nicolai Haehnle <nhaehnle@gmail.com> | 2016-04-19 21:58:22 +0000 |
|---|---|---|
| committer | Nicolai Haehnle <nhaehnle@gmail.com> | 2016-04-19 21:58:22 +0000 |
| commit | e2dda4f7500b135005f0c71b44ac900c3725c892 (patch) | |
| tree | bd35e80e29033e7c23c639f08db0273fa3c5a6df /llvm/lib/Target | |
| parent | 7483937bf0e36ef0afd34a3471e76901e0e49796 (diff) | |
| download | bcm5719-llvm-e2dda4f7500b135005f0c71b44ac900c3725c892.tar.gz bcm5719-llvm-e2dda4f7500b135005f0c71b44ac900c3725c892.zip | |
AMDGPU: Guard VOPC instructions against incorrect commute
Summary:
The added testcase, which triggered this, was derived from a shader-db case
via bugpoint. A separate question is why scalar branching wasn't used.
Reviewers: arsenm, tstellarAMD
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D19208
llvm-svn: 266825
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index d4099bfd538..fc7cb88c827 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -944,10 +944,10 @@ MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr *MI, MachineOperand &Src1 = MI->getOperand(Src1Idx); - if (isVOP2(*MI)) { + if (isVOP2(*MI) || isVOPC(*MI)) { const MCInstrDesc &InstrDesc = MI->getDesc(); - // For VOP2 instructions, any operand type is valid to use for src0. Make - // sure we can use the src1 as src0. + // For VOP2 and VOPC instructions, any operand type is valid to use for + // src0. Make sure we can use the src0 as src1. // // We could be stricter here and only allow commuting if there is a reason // to do so. i.e. if both operands are VGPRs there is no real benefit, |
