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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-27 19:24:47 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-02-27 19:24:47 +0000 |
| commit | e2d1d3a9403d2b096088d23e6ce8986607a465fe (patch) | |
| tree | 6d692df65437dfba3723cbfed043d51507772e22 /llvm/lib/Target | |
| parent | 0aadc6ef13bdf10c63ff19dfc4b29c673ab09a44 (diff) | |
| download | bcm5719-llvm-e2d1d3a9403d2b096088d23e6ce8986607a465fe.tar.gz bcm5719-llvm-e2d1d3a9403d2b096088d23e6ce8986607a465fe.zip | |
AMDGPU: Add f16 to shader calling conventions
Mostly useful for writing tests for f16 features.
llvm-svn: 296370
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td b/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td index 47dfa499206..6b9ebcfe0b7 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td @@ -17,7 +17,7 @@ class CCIfNotInReg<CCAction A> : CCIf<"!ArgFlags.isInReg()", A> {} // Calling convention for SI def CC_SI : CallingConv<[ - CCIfInReg<CCIfType<[f32, i32] , CCAssignToReg<[ + CCIfInReg<CCIfType<[f32, i32, f16] , CCAssignToReg<[ SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7, SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15, SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23, @@ -35,7 +35,7 @@ def CC_SI : CallingConv<[ >>>, // 32*4 + 4 is the minimum for a fetch shader consumer with 32 inputs. - CCIfNotInReg<CCIfType<[f32, i32] , CCAssignToReg<[ + CCIfNotInReg<CCIfType<[f32, i32, f16] , CCAssignToReg<[ VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15, VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23, @@ -76,7 +76,7 @@ def RetCC_SI : CallingConv<[ ]>>, // 32*4 + 4 is the minimum for a fetch shader with 32 outputs. - CCIfType<[f32] , CCAssignToReg<[ + CCIfType<[f32, f16] , CCAssignToReg<[ VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15, VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23, |
