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| author | Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com> | 2019-02-26 16:55:10 +0000 |
|---|---|---|
| committer | Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com> | 2019-02-26 16:55:10 +0000 |
| commit | e172d7008d0c12eaa9ee2aee16ee4e13c176553c (patch) | |
| tree | 8beb77f4f6a28e4e3c230c29202395f175c7a3ac /llvm/lib/Target | |
| parent | c110b5b69f19700939a56d08218dfb0abb577af9 (diff) | |
| download | bcm5719-llvm-e172d7008d0c12eaa9ee2aee16ee4e13c176553c.tar.gz bcm5719-llvm-e172d7008d0c12eaa9ee2aee16ee4e13c176553c.zip | |
[X86] AMD znver2 enablement
This patch enables the following
1) AMD family 17h "znver2" tune flag (-march, -mcpu).
2) ISAs that are enabled for "znver2" architecture.
3) For the time being, it uses the znver1 scheduler model.
4) Tests are updated.
5) Scheduler descriptions are yet to be put in place.
Reviewers: craig.topper
Differential Revision: https://reviews.llvm.org/D58343
llvm-svn: 354897
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86.td | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index 502278bd8a5..094790023b1 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -1143,8 +1143,8 @@ def : Proc<"bdver4", [ FeatureMacroFusion ]>; -// Znver1 -def: ProcessorModel<"znver1", Znver1Model, [ +// AMD Zen Processors common ISAs +def ZNFeatures : ProcessorFeatures<[], [ FeatureADX, FeatureAES, FeatureAVX2, @@ -1183,6 +1183,19 @@ def: ProcessorModel<"znver1", Znver1Model, [ FeatureXSAVEOPT, FeatureXSAVES]>; +class Znver1Proc<string Name> : ProcModel<Name, Znver1Model, + ZNFeatures.Value, [ +]>; +def : Znver1Proc<"znver1">; + +class Znver2Proc<string Name> : ProcModel<Name, Znver1Model, + ZNFeatures.Value, [ + FeatureCLWB, + FeatureRDPID, + FeatureWBNOINVD +]>; +def : Znver2Proc<"znver2">; + def : Proc<"geode", [FeatureX87, FeatureSlowUAMem16, Feature3DNowA]>; def : Proc<"winchip-c6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>; |
