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| author | Craig Topper <craig.topper@gmail.com> | 2016-05-22 06:09:34 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2016-05-22 06:09:34 +0000 |
| commit | de5498546e4e92865e904ae2c0779d736e8918c1 (patch) | |
| tree | 634489e8e0e4e071ad77c78acc8dbb225c028f7e /llvm/lib/Target | |
| parent | 5cfda6feb15a3765b97a06961623637772cb92fc (diff) | |
| download | bcm5719-llvm-de5498546e4e92865e904ae2c0779d736e8918c1.tar.gz bcm5719-llvm-de5498546e4e92865e904ae2c0779d736e8918c1.zip | |
[AVX512] Change the AddedComplexity on some patterns to match their AVX/SSE equivalents. This helps group them close together in the isel tables and enable table compression.
llvm-svn: 270354
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 2bbc9e76e92..def35bbef63 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -3138,14 +3138,21 @@ def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst), EVEX_CD8<8, CD8VT8>; let Predicates = [HasAVX512] in { + let AddedComplexity = 15 in { + def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))), + (VMOVDI2PDIZrr GR32:$src)>; + + def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))), + (VMOV64toPQIZrr GR64:$src)>; + + def : Pat<(v4i64 (X86vzmovl (insert_subvector undef, + (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))), + (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>; + } // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part. let AddedComplexity = 20 in { def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))), (VMOVDI2PDIZrm addr:$src)>; - def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))), - (VMOV64toPQIZrr GR64:$src)>; - def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))), - (VMOVDI2PDIZrr GR32:$src)>; def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))), (VMOVDI2PDIZrm addr:$src)>; @@ -3157,17 +3164,14 @@ let Predicates = [HasAVX512] in { (VMOVZPQILo2PQIZrr VR128X:$src)>; def : Pat<(v2i64 (X86vzload addr:$src)), (VMOVZPQILo2PQIZrm addr:$src)>; + def : Pat<(v4i64 (X86vzload addr:$src)), + (SUBREG_TO_REG (i64 0), (VMOVZPQILo2PQIZrm addr:$src), sub_xmm)>; } // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext. def : Pat<(v8i32 (X86vzmovl (insert_subvector undef, (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))), (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>; - def : Pat<(v4i64 (X86vzmovl (insert_subvector undef, - (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))), - (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>; - def : Pat<(v4i64 (X86vzload addr:$src)), - (SUBREG_TO_REG (i64 0), (VMOVZPQILo2PQIZrm addr:$src), sub_xmm)>; // Use regular 128-bit instructions to match 512-bit scalar_to_vec+zext. def : Pat<(v8i64 (X86vzload addr:$src)), |
