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| author | Amara Emerson <aemerson@apple.com> | 2019-04-17 21:30:07 +0000 | 
|---|---|---|
| committer | Amara Emerson <aemerson@apple.com> | 2019-04-17 21:30:07 +0000 | 
| commit | daf6e66ac5d2f5305f493e90923d11b91a27e7b3 (patch) | |
| tree | 7badd822a22c91cbe01953972deb685caff1565f /llvm/lib/Target | |
| parent | aa4eb10a7abe712a048f31aa22c0657a91143088 (diff) | |
| download | bcm5719-llvm-daf6e66ac5d2f5305f493e90923d11b91a27e7b3.tar.gz bcm5719-llvm-daf6e66ac5d2f5305f493e90923d11b91a27e7b3.zip | |
[GlobalISel] Add legalization support for non-power-2 loads and stores
Legalize things like i24 load/store by splitting them into smaller power of 2 operations.
This matches how SelectionDAG handles these operations.
Differential Revision: https://reviews.llvm.org/D59971
llvm-svn: 358613
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp | 13 | 
1 files changed, 5 insertions, 8 deletions
| diff --git a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp index 85110b2ec76..8f7a521b559 100644 --- a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp @@ -234,14 +234,12 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {        .legalForTypesWithMemDesc({{s32, p0, 8, 8},                                   {s32, p0, 16, 8}})        .clampScalar(0, s8, s64) -      .widenScalarToNextPow2(0) -      // TODO: We could support sum-of-pow2's but the lowering code doesn't know -      //       how to do that yet. -      .unsupportedIfMemSizeNotPow2() +      .lowerIfMemSizeNotPow2()        // Lower any any-extending loads left into G_ANYEXT and G_LOAD        .lowerIf([=](const LegalityQuery &Query) {          return Query.Types[0].getSizeInBits() != Query.MMODescrs[0].SizeInBits;        }) +      .widenScalarToNextPow2(0)        .clampMaxNumElements(0, s32, 2)        .clampMaxNumElements(0, s64, 1)        .customIf(IsPtrVecPred); @@ -249,6 +247,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {    getActionDefinitionsBuilder(G_STORE)        .legalForTypesWithMemDesc({{s8, p0, 8, 8},                                   {s16, p0, 16, 8}, +                                 {s32, p0, 8, 8}, +                                 {s32, p0, 16, 8},                                   {s32, p0, 32, 8},                                   {s64, p0, 64, 8},                                   {p0, p0, 64, 8}, @@ -259,10 +259,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {                                   {v4s32, p0, 128, 8},                                   {v2s64, p0, 128, 8}})        .clampScalar(0, s8, s64) -      .widenScalarToNextPow2(0) -      // TODO: We could support sum-of-pow2's but the lowering code doesn't know -      //       how to do that yet. -      .unsupportedIfMemSizeNotPow2() +      .lowerIfMemSizeNotPow2()        .lowerIf([=](const LegalityQuery &Query) {          return Query.Types[0].isScalar() &&                 Query.Types[0].getSizeInBits() != Query.MMODescrs[0].SizeInBits; | 

