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authorJames Y Knight <jyknight@google.com>2015-08-19 14:47:04 +0000
committerJames Y Knight <jyknight@google.com>2015-08-19 14:47:04 +0000
commitd966fb6fef351da66768cbe560c90dceeb6bf07a (patch)
treeb0ed5be4eac5c0211b1bef42f9dc5f5c58e22a89 /llvm/lib/Target
parent494abf1ad8d4771b0d15ae1437b39e26aa69a7bf (diff)
downloadbcm5719-llvm-d966fb6fef351da66768cbe560c90dceeb6bf07a.tar.gz
bcm5719-llvm-d966fb6fef351da66768cbe560c90dceeb6bf07a.zip
[SPARC] Fix BooleanContents, so that select of a trunc doesn't
eliminate the trunc. Differential Revision: http://reviews.llvm.org/D10442 llvm-svn: 245444
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/Sparc/SparcISelLowering.cpp8
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 1811631d6b3..9c8a0a64525 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -1423,6 +1423,14 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM,
: TargetLowering(TM), Subtarget(&STI) {
MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
+ // Instructions which use registers as conditionals examine all the
+ // bits (as does the pseudo SELECT_CC expansion). I don't think it
+ // matters much whether it's ZeroOrOneBooleanContent, or
+ // ZeroOrNegativeOneBooleanContent, so, arbitrarily choose the
+ // former.
+ setBooleanContents(ZeroOrOneBooleanContent);
+ setBooleanVectorContents(ZeroOrOneBooleanContent);
+
// Set up the register classes.
addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
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