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| author | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2014-12-15 16:19:34 +0000 |
|---|---|---|
| committer | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2014-12-15 16:19:34 +0000 |
| commit | d7ecf49e97699078cbd1ee24e8bd6ee0a5f746c7 (patch) | |
| tree | ec957cb0b8e0ca903244ef96c5a69d46ca956718 /llvm/lib/Target | |
| parent | 19703a0bd65c090c556c9365890b2d6191bcf626 (diff) | |
| download | bcm5719-llvm-d7ecf49e97699078cbd1ee24e8bd6ee0a5f746c7.tar.gz bcm5719-llvm-d7ecf49e97699078cbd1ee24e8bd6ee0a5f746c7.zip | |
Add disassembler tests for mips3 platform. There are no functional changes.
llvm-svn: 224253
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 81bbe3003e2..ec90781f629 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -1055,7 +1055,8 @@ static DecodeStatus DecodeMem(MCInst &Inst, Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); Base = getReg(Decoder, Mips::GPR32RegClassID, Base); - if(Inst.getOpcode() == Mips::SC){ + if(Inst.getOpcode() == Mips::SC || + Inst.getOpcode() == Mips::SCD){ Inst.addOperand(MCOperand::CreateReg(Reg)); } |
