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authorZoran Jovanovic <zoran.jovanovic@imgtec.com>2016-01-29 16:18:34 +0000
committerZoran Jovanovic <zoran.jovanovic@imgtec.com>2016-01-29 16:18:34 +0000
commitd474ef3a3b257fb8019833db5d8da4abcf4ee988 (patch)
tree9382c62685760c435f2b31db40d2b74284204e67 /llvm/lib/Target
parent23f12e5c029273fd008837c6b8d36b00e1e20de8 (diff)
downloadbcm5719-llvm-d474ef3a3b257fb8019833db5d8da4abcf4ee988.tar.gz
bcm5719-llvm-d474ef3a3b257fb8019833db5d8da4abcf4ee988.zip
[mips] Absolute value macro expansion
Author: obucina Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D16323 llvm-svn: 259202
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp22
-rw-r--r--llvm/lib/Target/Mips/MipsInstrInfo.td3
2 files changed, 25 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index a13d1d794ab..192b3444936 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -233,6 +233,9 @@ class MipsAsmParser : public MCTargetAsmParser {
bool expandDRotationImm(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions);
+ bool expandAbs(MCInst &Inst, SMLoc IDLoc,
+ SmallVectorImpl<MCInst> &Instructions);
+
void createNop(bool hasShortDelaySlot, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions);
@@ -2087,6 +2090,9 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc,
case Mips::DRORImm:
return expandDRotationImm(Inst, IDLoc, Instructions) ? MER_Fail
: MER_Success;
+ case Mips::ABSMacro:
+ return expandAbs(Inst, IDLoc, Instructions) ? MER_Fail
+ : MER_Success;
}
}
@@ -3531,6 +3537,22 @@ bool MipsAsmParser::expandDRotationImm(MCInst &Inst, SMLoc IDLoc,
return true;
}
+bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc,
+ SmallVectorImpl<MCInst> &Instructions) {
+
+ unsigned FirstRegOp = Inst.getOperand(0).getReg();
+ unsigned SecondRegOp = Inst.getOperand(1).getReg();
+
+ emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, Instructions);
+ if (FirstRegOp != SecondRegOp)
+ emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, Instructions);
+ else
+ createNop(false, IDLoc, Instructions);
+ emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, Instructions);
+
+ return false;
+}
+
void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) {
if (hasShortDelaySlot)
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index ffda491f0c8..c5a314fe2d8 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -1808,6 +1808,9 @@ def : MipsInstAlias<"dror $rd, $rs",
def : MipsInstAlias<"dror $rd, $imm",
(DRORImm GPR32Opnd:$rd, GPR32Opnd:$rd, simm16:$imm), 0>, ISA_MIPS64;
+def ABSMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
+ "abs\t$rd, $rs">;
+
//===----------------------------------------------------------------------===//
// Instruction aliases
//===----------------------------------------------------------------------===//
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