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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-02-19 15:22:47 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-02-19 15:22:47 +0000 |
| commit | d4409e2cecc376b7226e125fa2bbf9005649e2e3 (patch) | |
| tree | c8692b86e2e4426aef82b36056fb42d78bf1c688 /llvm/lib/Target | |
| parent | a24a5167379cf32c6622cf151a9b77c1588faabc (diff) | |
| download | bcm5719-llvm-d4409e2cecc376b7226e125fa2bbf9005649e2e3.tar.gz bcm5719-llvm-d4409e2cecc376b7226e125fa2bbf9005649e2e3.zip | |
R600: Add AR_X to the R600_TReg_X register class.
NOTE: This is a candidate for the Mesa stable branch.
llvm-svn: 175519
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/R600/R600RegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/R600/R600RegisterInfo.td b/llvm/lib/Target/R600/R600RegisterInfo.td index 071885465a0..ce5994ca368 100644 --- a/llvm/lib/Target/R600/R600RegisterInfo.td +++ b/llvm/lib/Target/R600/R600RegisterInfo.td @@ -81,7 +81,7 @@ def R600_Addr : RegisterClass <"AMDGPU", [i32], 127, (add (sequence "Addr%u_X", } // End isAllocatable = 0 def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32, - (add (sequence "T%u_X", 0, 127))>; + (add (sequence "T%u_X", 0, 127), AR_X)>; def R600_TReg32_Y : RegisterClass <"AMDGPU", [f32, i32], 32, (add (sequence "T%u_Y", 0, 127))>; |
