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| author | Evan Cheng <evan.cheng@apple.com> | 2010-07-26 21:50:05 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-07-26 21:50:05 +0000 |
| commit | d4218b8793563fcfaaec301dc6c556a27de22f3b (patch) | |
| tree | ce1ccc145867fe4e43d4f6052024da04fee10a17 /llvm/lib/Target | |
| parent | e6d6c5dd11d4d760c0781678b86515ae30b160c3 (diff) | |
| download | bcm5719-llvm-d4218b8793563fcfaaec301dc6c556a27de22f3b.tar.gz bcm5719-llvm-d4218b8793563fcfaaec301dc6c556a27de22f3b.zip | |
On x86, f32 / f64 nodes share the same registers as 128-bit vector values.
llvm-svn: 109450
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 26 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.h | 4 |
2 files changed, 30 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index c808ffa6f06..618bb90d445 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -1190,6 +1190,32 @@ unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const { return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4; } +std::pair<const TargetRegisterClass*, uint8_t> +X86TargetLowering::findRepresentativeClass(EVT VT) const{ + const TargetRegisterClass *RRC = 0; + uint8_t Cost = 1; + switch (VT.getSimpleVT().SimpleTy) { + default: + return TargetLowering::findRepresentativeClass(VT); + case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: + RRC = (Subtarget->is64Bit() + ? X86::GR64RegisterClass : X86::GR32RegisterClass); + break; + case MVT::v8i8: case MVT::v4i16: + case MVT::v2i32: case MVT::v1i64: + RRC = X86::VR64RegisterClass; + break; + case MVT::f32: case MVT::f64: + case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: + case MVT::v4f32: case MVT::v2f64: + case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: + case MVT::v4f64: + RRC = X86::VR128RegisterClass; + break; + } + return std::make_pair(RRC, Cost); +} + unsigned X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const { diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h index f43b8765059..96c97d9f9ef 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -599,6 +599,10 @@ namespace llvm { /// appropriate. virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const; + protected: + std::pair<const TargetRegisterClass*, uint8_t> + findRepresentativeClass(EVT VT) const; + private: /// Subtarget - Keep a pointer to the X86Subtarget around so that we can /// make the right decision when generating code for different targets. |

