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| author | Tom Stellard <thomas.stellard@amd.com> | 2015-05-12 14:18:11 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2015-05-12 14:18:11 +0000 |
| commit | d33d7f15a26208225b7cfbbe5eda2e28cdf82a11 (patch) | |
| tree | f6fe858b2fe0044f89d33e862ea48828e94573fd /llvm/lib/Target | |
| parent | 79cc3eda1ee18e10661ca0209fc90e5d9076abd4 (diff) | |
| download | bcm5719-llvm-d33d7f15a26208225b7cfbbe5eda2e28cdf82a11.tar.gz bcm5719-llvm-d33d7f15a26208225b7cfbbe5eda2e28cdf82a11.zip | |
R600/SI: Replace TRI->getRegClass(Reg) with TRI->getPhysRegClass(Reg)
TRI->getRegClass() takes a register class ID, not a register. We were
using this incorrectly in a few places.
llvm-svn: 237132
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/R600/SIFixSGPRCopies.cpp | 13 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/SIFoldOperands.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/SIRegisterInfo.cpp | 1 |
3 files changed, 11 insertions, 7 deletions
diff --git a/llvm/lib/Target/R600/SIFixSGPRCopies.cpp b/llvm/lib/Target/R600/SIFixSGPRCopies.cpp index cd1b3acc5c8..142b1433265 100644 --- a/llvm/lib/Target/R600/SIFixSGPRCopies.cpp +++ b/llvm/lib/Target/R600/SIFixSGPRCopies.cpp @@ -140,7 +140,7 @@ const TargetRegisterClass *SIFixSGPRCopies::inferRegClassFromUses( const TargetRegisterClass *RC = TargetRegisterInfo::isVirtualRegister(Reg) ? MRI.getRegClass(Reg) : - TRI->getRegClass(Reg); + TRI->getPhysRegClass(Reg); RC = TRI->getSubRegClass(RC, SubReg); for (MachineRegisterInfo::use_instr_iterator @@ -183,10 +183,13 @@ bool SIFixSGPRCopies::isVGPRToSGPRCopy(const MachineInstr &Copy, unsigned SrcReg = Copy.getOperand(1).getReg(); unsigned SrcSubReg = Copy.getOperand(1).getSubReg(); - const TargetRegisterClass *DstRC - = TargetRegisterInfo::isVirtualRegister(DstReg) ? - MRI.getRegClass(DstReg) : - TRI->getRegClass(DstReg); + if (!TargetRegisterInfo::isVirtualRegister(DstReg)) { + // If the destination register is a physical register there isn't really + // much we can do to fix this. + return false; + } + + const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg); const TargetRegisterClass *SrcRC; diff --git a/llvm/lib/Target/R600/SIFoldOperands.cpp b/llvm/lib/Target/R600/SIFoldOperands.cpp index 7ba5a6d7c38..d14e37a6461 100644 --- a/llvm/lib/Target/R600/SIFoldOperands.cpp +++ b/llvm/lib/Target/R600/SIFoldOperands.cpp @@ -216,7 +216,7 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) { const TargetRegisterClass *UseRC = TargetRegisterInfo::isVirtualRegister(UseReg) ? MRI.getRegClass(UseReg) : - TRI.getRegClass(UseReg); + TRI.getPhysRegClass(UseReg); Imm = APInt(64, OpToFold.getImm()); @@ -240,7 +240,7 @@ bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) { const TargetRegisterClass *DestRC = TargetRegisterInfo::isVirtualRegister(DestReg) ? MRI.getRegClass(DestReg) : - TRI.getRegClass(DestReg); + TRI.getPhysRegClass(DestReg); unsigned MovOp = TII->getMovOpcode(DestRC); if (MovOp == AMDGPU::COPY) diff --git a/llvm/lib/Target/R600/SIRegisterInfo.cpp b/llvm/lib/Target/R600/SIRegisterInfo.cpp index 13a89743677..3529cd0449c 100644 --- a/llvm/lib/Target/R600/SIRegisterInfo.cpp +++ b/llvm/lib/Target/R600/SIRegisterInfo.cpp @@ -347,6 +347,7 @@ const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const { assert(!TargetRegisterInfo::isVirtualRegister(Reg)); static const TargetRegisterClass *BaseClasses[] = { + &AMDGPU::M0RegRegClass, &AMDGPU::VGPR_32RegClass, &AMDGPU::SReg_32RegClass, &AMDGPU::VReg_64RegClass, |
