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authorStrahinja Petrovic <strahinja.petrovic@rt-rk.com>2017-06-21 09:25:51 +0000
committerStrahinja Petrovic <strahinja.petrovic@rt-rk.com>2017-06-21 09:25:51 +0000
commitd280ea4f763786cfe037af6bc7baec0614017e97 (patch)
tree93567b4142f8ada0ebc4d0f56899abedf696f1c2 /llvm/lib/Target
parente3a0cc2ca06e45bbbd9a1f6eeddca53e4ca1f579 (diff)
downloadbcm5719-llvm-d280ea4f763786cfe037af6bc7baec0614017e97.tar.gz
bcm5719-llvm-d280ea4f763786cfe037af6bc7baec0614017e97.zip
[MIPS] Fix for selecting of DINS/INS instruction
This patch adds one more condition in selection DINS/INS instruction, which fixes MultiSource/Applications/JM/ldecod/ for mips32r2 (and mips64r2 n32 abi). Differential Revision: https://reviews.llvm.org/D33725 llvm-svn: 305888
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/Mips/MipsISelLowering.cpp5
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 68708dc4f50..02102d6b22f 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -907,6 +907,11 @@ static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1))))
return SDValue();
}
+ // Don't generate INS if constant OR operand doesn't fit into bits
+ // cleared by constant AND operand.
+ if (CN->getSExtValue() & CN1->getSExtValue())
+ return SDValue();
+
SDLoc DL(N);
EVT ValTy = N->getOperand(0)->getValueType(0);
SDValue Const1;
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